/* Generated automatically by the program `genemit'
from the machine description file `md'.  */

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "backend.h"
#include "predict.h"
#include "tree.h"
#include "rtl.h"
#include "alias.h"
#include "varasm.h"
#include "stor-layout.h"
#include "calls.h"
#include "tm_p.h"
#include "flags.h"
#include "insn-config.h"
#include "expmed.h"
#include "dojump.h"
#include "explow.h"
#include "emit-rtl.h"
#include "stmt.h"
#include "expr.h"
#include "insn-codes.h"
#include "optabs.h"
#include "dfp.h"
#include "output.h"
#include "recog.h"
#include "df.h"
#include "resource.h"
#include "reload.h"
#include "diagnostic-core.h"
#include "regs.h"
#include "tm-constrs.h"
#include "ggc.h"
#include "dumpfile.h"
#include "target.h"

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:227 */
rtx
gen_indirect_jump (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	operand0);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:234 */
rtx
gen_jump (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	gen_rtx_LABEL_REF (VOIDmode,
	operand0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:279 */
rtx
gen_ccmpsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCmode,
	gen_rtvec (1,
		operand5),
	67)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:279 */
rtx
gen_ccmpdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCmode,
	gen_rtvec (1,
		operand5),
	67)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:297 */
rtx
gen_fccmpsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCFPmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCFPmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCFPmode,
	gen_rtvec (1,
		operand5),
	67)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:297 */
rtx
gen_fccmpdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCFPmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCFPmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCFPmode,
	gen_rtvec (1,
		operand5),
	67)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:312 */
rtx
gen_fccmpesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCFPEmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCFPEmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCFPEmode,
	gen_rtvec (1,
		operand5),
	67)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:312 */
rtx
gen_fccmpedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand1,
	gen_rtx_IF_THEN_ELSE (CCFPEmode,
	gen_rtx_fmt_ee (GET_CODE (operand4), VOIDmode,
		operand0,
		const0_rtx),
	gen_rtx_COMPARE (CCFPEmode,
	operand2,
	operand3),
	gen_rtx_UNSPEC (CCFPEmode,
	gen_rtvec (1,
		operand5),
	67)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:383 */
rtx
gen_condjump (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		const0_rtx),
	gen_rtx_LABEL_REF (VOIDmode,
	operand2),
	pc_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:489 */
rtx
gen_casesi_dispatch (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (pc_rtx,
	gen_rtx_MEM (DImode,
	gen_rtx_UNSPEC (VOIDmode,
	gen_rtvec (2,
		operand0,
		operand1),
	0))),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_USE (VOIDmode,
	gen_rtx_LABEL_REF (VOIDmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:507 */
rtx
gen_nop (void)
{
  return gen_rtx_UNSPEC (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	38);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:514 */
rtx
gen_prefetch (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PREFETCH (VOIDmode,
	operand0,
	operand1,
	operand2);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:541 */
rtx
gen_trap (void)
{
  return gen_rtx_TRAP_IF (VOIDmode,
	const1_rtx,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:587 */
rtx
gen_simple_return (void)
{
  return simple_return_rtx;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:594 */
rtx
gen_eh_return (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		operand0),
	0);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1093 */
rtx
gen_insv_immsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_ZERO_EXTRACT (SImode,
	operand0,
	const_int_rtx[MAX_SAVED_CONST_INT + (16)],
	operand1),
	operand2);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1093 */
rtx
gen_insv_immdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_ZERO_EXTRACT (DImode,
	operand0,
	const_int_rtx[MAX_SAVED_CONST_INT + (16)],
	operand1),
	operand2);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1287 */
rtx
gen_load_pairsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1303 */
rtx
gen_load_pairdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1322 */
rtx
gen_store_pairsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1338 */
rtx
gen_store_pairdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1356 */
rtx
gen_load_pairsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1372 */
rtx
gen_load_pairdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1390 */
rtx
gen_store_pairsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1406 */
rtx
gen_store_pairdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1424 */
rtx
gen_loadwb_pairsi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (SImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (SImode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1424 */
rtx
gen_loadwb_pairsi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (SImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (SImode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1424 */
rtx
gen_loadwb_pairdi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (DImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (DImode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1424 */
rtx
gen_loadwb_pairdi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (DImode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (DImode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1439 */
rtx
gen_loadwb_pairsf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (SFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1439 */
rtx
gen_loadwb_pairsf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (SFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1439 */
rtx
gen_loadwb_pairdf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (DFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1439 */
rtx
gen_loadwb_pairdf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (operand2,
	gen_rtx_MEM (DFmode,
	operand1)),
		gen_rtx_SET (operand3,
	gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand5)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1456 */
rtx
gen_storewb_pairsi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (SImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (SImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1456 */
rtx
gen_storewb_pairsi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (SImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (SImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1456 */
rtx
gen_storewb_pairdi_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (DImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (DImode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1456 */
rtx
gen_storewb_pairdi_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (DImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (DImode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1472 */
rtx
gen_storewb_pairsf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1472 */
rtx
gen_storewb_pairsf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (SFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1472 */
rtx
gen_storewb_pairdf_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (SImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1472 */
rtx
gen_storewb_pairdf_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand4)),
		gen_rtx_SET (gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand4)),
	operand2),
		gen_rtx_SET (gen_rtx_MEM (DFmode,
	gen_rtx_PLUS (DImode,
	operand0,
	operand5)),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1742 */
rtx
gen_addsi3_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1742 */
rtx
gen_adddi3_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1825 */
rtx
gen_addsi3_compareC (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Cmode,
	66),
	gen_rtx_NE (CC_Cmode,
	gen_rtx_PLUS (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2)),
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1825 */
rtx
gen_adddi3_compareC (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_Cmode,
	66),
	gen_rtx_NE (CC_Cmode,
	gen_rtx_PLUS (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_ZERO_EXTEND (TImode,
	operand2)),
	gen_rtx_ZERO_EXTEND (TImode,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2))))),
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2263 */
rtx
gen_subsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2283 */
rtx
gen_subdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2339 */
rtx
gen_subsi3_compare1 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand1,
	operand2)),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2339 */
rtx
gen_subdi3_compare1 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand1,
	operand2)),
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	copy_rtx (operand1),
	copy_rtx (operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2642 */
rtx
gen_negsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2642 */
rtx
gen_negdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2683 */
rtx
gen_negsi2_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_NEG (SImode,
	operand1),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	copy_rtx (operand1)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2683 */
rtx
gen_negdi2_compare0 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (gen_rtx_REG (CC_NZmode,
	66),
	gen_rtx_COMPARE (CC_NZmode,
	gen_rtx_NEG (DImode,
	operand1),
	const0_rtx)),
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	copy_rtx (operand1)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2764 */
rtx
gen_mulsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2764 */
rtx
gen_muldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2784 */
rtx
gen_maddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_MULT (SImode,
	operand1,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2784 */
rtx
gen_madddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_MULT (DImode,
	operand1,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2852 */
rtx
gen_mulsidi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2852 */
rtx
gen_umulsidi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2861 */
rtx
gen_maddsidi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2861 */
rtx
gen_umaddsidi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2872 */
rtx
gen_msubsidi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand3,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2872 */
rtx
gen_umsubsidi4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand3,
	gen_rtx_MULT (DImode,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (DImode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2936 */
rtx
gen_smuldi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (DImode,
	gen_rtx_LSHIFTRT (TImode,
	gen_rtx_MULT (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (64)])));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2936 */
rtx
gen_umuldi3_highpart (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (DImode,
	gen_rtx_LSHIFTRT (TImode,
	gen_rtx_MULT (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_ZERO_EXTEND (TImode,
	operand2)),
	const_int_rtx[MAX_SAVED_CONST_INT + (64)])));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2949 */
rtx
gen_divsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2949 */
rtx
gen_udivsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UDIV (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2949 */
rtx
gen_divdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_DIV (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2949 */
rtx
gen_udivdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UDIV (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2973 */
rtx
gen_cmpsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2973 */
rtx
gen_cmpdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_COMPARE (CCmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2985 */
rtx
gen_fcmpsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCFPmode,
	66),
	gen_rtx_COMPARE (CCFPmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2985 */
rtx
gen_fcmpdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCFPmode,
	66),
	gen_rtx_COMPARE (CCFPmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2996 */
rtx
gen_fcmpesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCFPEmode,
	66),
	gen_rtx_COMPARE (CCFPEmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2996 */
rtx
gen_fcmpedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_REG (CCFPEmode,
	66),
	gen_rtx_COMPARE (CCFPEmode,
	operand0,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3082 */
rtx
gen_aarch64_cstoreqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), QImode,
		operand2,
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3082 */
rtx
gen_aarch64_cstorehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), HImode,
		operand2,
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3082 */
rtx
gen_aarch64_cstoresi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3082 */
rtx
gen_aarch64_cstoredi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), DImode,
		operand2,
		const0_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3136 */
rtx
gen_cstoreqi_neg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (QImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), QImode,
		operand2,
		const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3136 */
rtx
gen_cstorehi_neg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), HImode,
		operand2,
		const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3136 */
rtx
gen_cstoresi_neg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3136 */
rtx
gen_cstoredi_neg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), DImode,
		operand2,
		const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3333 */
rtx
gen_aarch64_crc32b (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3333 */
rtx
gen_aarch64_crc32h (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	6));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3333 */
rtx
gen_aarch64_crc32w (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	7));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3333 */
rtx
gen_aarch64_crc32x (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	8));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3333 */
rtx
gen_aarch64_crc32cb (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3333 */
rtx
gen_aarch64_crc32ch (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3333 */
rtx
gen_aarch64_crc32cw (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	4));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3333 */
rtx
gen_aarch64_crc32cx (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	5));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3357 */
rtx
gen_csinc3si_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_PLUS (SImode,
	operand2,
	const1_rtx),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3357 */
rtx
gen_csinc3di_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	gen_rtx_PLUS (DImode,
	operand2,
	const1_rtx),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3380 */
rtx
gen_csneg3_uxtw_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_NEG (SImode,
	operand2),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3392 */
rtx
gen_csneg3si_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_NEG (SImode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3392 */
rtx
gen_csneg3di_insn (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	gen_rtx_NEG (DImode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3407 */
rtx
gen_andsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3407 */
rtx
gen_iorsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3407 */
rtx
gen_xorsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3407 */
rtx
gen_anddi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3407 */
rtx
gen_iordi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3407 */
rtx
gen_xordi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3543 */
rtx
gen_one_cmplsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3543 */
rtx
gen_one_cmpldi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_and_one_cmpl_ashlsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_and_one_cmpl_ashrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_and_one_cmpl_lshrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_and_one_cmpl_rotrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_ior_one_cmpl_ashlsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_ior_one_cmpl_ashrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_ior_one_cmpl_lshrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_ior_one_cmpl_rotrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_xor_one_cmpl_ashlsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_xor_one_cmpl_ashrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_xor_one_cmpl_lshrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_xor_one_cmpl_rotrsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	gen_rtx_NOT (SImode,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_and_one_cmpl_ashldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_and_one_cmpl_ashrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_and_one_cmpl_lshrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_and_one_cmpl_rotrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_ior_one_cmpl_ashldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_ior_one_cmpl_ashrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_ior_one_cmpl_lshrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_ior_one_cmpl_rotrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_xor_one_cmpl_ashldi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_xor_one_cmpl_ashrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_xor_one_cmpl_lshrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3658 */
rtx
gen_xor_one_cmpl_rotrdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_NOT (DImode,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3747 */
rtx
gen_clzsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3747 */
rtx
gen_clzdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3770 */
rtx
gen_clrsbsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3770 */
rtx
gen_clrsbdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3778 */
rtx
gen_rbitsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	40));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3778 */
rtx
gen_rbitdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	40));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3791 */
rtx
gen_ctzsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CTZ (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3791 */
rtx
gen_ctzdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CTZ (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4395 */
rtx
gen_bswapsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4395 */
rtx
gen_bswapdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4403 */
rtx
gen_bswaphi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4415 */
rtx
gen_rev16si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_AND (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand3),
	gen_rtx_AND (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4415 */
rtx
gen_rev16di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_AND (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand3),
	gen_rtx_AND (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4429 */
rtx
gen_rev16si2_alt (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	gen_rtx_AND (SImode,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand2),
	gen_rtx_AND (SImode,
	gen_rtx_ASHIFT (SImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4429 */
rtx
gen_rev16di2_alt (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	gen_rtx_AND (DImode,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand2),
	gen_rtx_AND (DImode,
	gen_rtx_ASHIFT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (8)]),
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_btrunchf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_ceilhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_floorhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_frintnhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_nearbyinthf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_rinthf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_roundhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	15));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_btruncsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_ceilsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_floorsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_frintnsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_nearbyintsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_rintsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_roundsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	15));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_btruncdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_ceildf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_floordf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_frintndf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_nearbyintdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_rintdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4459 */
rtx
gen_rounddf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	15));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtrunchfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceilhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloorhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lroundhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncuhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceiluhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lflooruhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lrounduhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnuhfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtrunchfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceilhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloorhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lroundhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncuhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceiluhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lflooruhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lrounduhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnuhfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceilsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloorsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lroundsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceilusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloorusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lroundusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnusfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceilsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloorsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lroundsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceilusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloorusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lroundusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnusfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceildfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloordfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lrounddfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintndfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncudfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceiludfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloorudfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lroundudfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnudfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceildfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloordfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lrounddfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintndfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lbtruncudfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lceiludfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfloorudfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lroundudfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4470 */
rtx
gen_lfrintnudfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4501 */
rtx
gen_fmahf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (HFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4501 */
rtx
gen_fmasf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4501 */
rtx
gen_fmadf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4511 */
rtx
gen_fnmahf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (HFmode,
	gen_rtx_NEG (HFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4511 */
rtx
gen_fnmasf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	gen_rtx_NEG (SFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4511 */
rtx
gen_fnmadf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	gen_rtx_NEG (DFmode,
	operand1),
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4522 */
rtx
gen_fmssf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	operand1,
	operand2,
	gen_rtx_NEG (SFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4522 */
rtx
gen_fmsdf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	operand1,
	operand2,
	gen_rtx_NEG (DFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4532 */
rtx
gen_fnmssf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (SFmode,
	gen_rtx_NEG (SFmode,
	operand1),
	operand2,
	gen_rtx_NEG (SFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4532 */
rtx
gen_fnmsdf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (DFmode,
	gen_rtx_NEG (DFmode,
	operand1),
	operand2,
	gen_rtx_NEG (DFmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4557 */
rtx
gen_extendsfdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4565 */
rtx
gen_extendhfsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4573 */
rtx
gen_extendhfdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4581 */
rtx
gen_truncdfsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4589 */
rtx
gen_truncsfhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4597 */
rtx
gen_truncdfhf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fix_trunchfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fixuns_trunchfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fix_trunchfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fixuns_trunchfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fix_truncsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fixuns_truncsfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fix_truncsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fixuns_truncsfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fix_truncdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fixuns_truncdfsi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fix_truncdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4605 */
rtx
gen_fixuns_truncdfdi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4613 */
rtx
gen_floatsisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4613 */
rtx
gen_floatunssisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4613 */
rtx
gen_floatdidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4613 */
rtx
gen_floatunsdidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4625 */
rtx
gen_floatdisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4625 */
rtx
gen_floatunsdisf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4625 */
rtx
gen_floatsidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4625 */
rtx
gen_floatunssidf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4633 */
rtx
gen_floatsihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4633 */
rtx
gen_floatunssihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4633 */
rtx
gen_floatdihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4633 */
rtx
gen_floatunsdihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4643 */
rtx
gen_fcvtzssf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4643 */
rtx
gen_fcvtzusf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4643 */
rtx
gen_fcvtzsdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4643 */
rtx
gen_fcvtzudf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4657 */
rtx
gen_scvtfsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4657 */
rtx
gen_ucvtfsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4657 */
rtx
gen_scvtfdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4657 */
rtx
gen_ucvtfdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4671 */
rtx
gen_fcvtzshfsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4671 */
rtx
gen_fcvtzuhfsi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4671 */
rtx
gen_fcvtzshfdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4671 */
rtx
gen_fcvtzuhfdi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4681 */
rtx
gen_scvtfsihf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4681 */
rtx
gen_ucvtfsihf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4681 */
rtx
gen_scvtfdihf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4681 */
rtx
gen_ucvtfdihf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4691 */
rtx
gen_fcvtzshf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4691 */
rtx
gen_fcvtzuhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4701 */
rtx
gen_scvtfhi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4701 */
rtx
gen_ucvtfhi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4715 */
rtx
gen_addhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4715 */
rtx
gen_addsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4715 */
rtx
gen_adddf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4725 */
rtx
gen_subhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4725 */
rtx
gen_subsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4725 */
rtx
gen_subdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4735 */
rtx
gen_mulhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4735 */
rtx
gen_mulsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4735 */
rtx
gen_muldf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4786 */
rtx
gen_neghf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4786 */
rtx
gen_negsf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4786 */
rtx
gen_negdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4811 */
rtx
gen_abshf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4811 */
rtx
gen_abssf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4811 */
rtx
gen_absdf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4823 */
rtx
gen_smaxsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4823 */
rtx
gen_smaxdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4832 */
rtx
gen_sminsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4832 */
rtx
gen_smindf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_smax_nanhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_smin_nanhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	74));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_fmaxhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	169));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_fminhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	170));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_smax_nansf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_smin_nansf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	74));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_fmaxsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	169));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_fminsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	170));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_smax_nandf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_smin_nandf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	74));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_fmaxdf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	169));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4844 */
rtx
gen_fmindf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	170));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4950 */
rtx
gen_aarch64_movdi_tilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4950 */
rtx
gen_aarch64_movdi_tflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4960 */
rtx
gen_aarch64_movdi_tihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const_int_rtx[MAX_SAVED_CONST_INT + (64)]));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4960 */
rtx
gen_aarch64_movdi_tfhigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const_int_rtx[MAX_SAVED_CONST_INT + (64)]));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4970 */
rtx
gen_aarch64_movtihigh_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_ZERO_EXTRACT (TImode,
	operand0,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const_int_rtx[MAX_SAVED_CONST_INT + (64)]),
	gen_rtx_ZERO_EXTEND (TImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4970 */
rtx
gen_aarch64_movtfhigh_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_ZERO_EXTRACT (TFmode,
	operand0,
	const_int_rtx[MAX_SAVED_CONST_INT + (64)],
	const_int_rtx[MAX_SAVED_CONST_INT + (64)]),
	gen_rtx_ZERO_EXTEND (TFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4980 */
rtx
gen_aarch64_movtilow_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4980 */
rtx
gen_aarch64_movtflow_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (TFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4989 */
rtx
gen_aarch64_movtilow_tilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (TImode,
	gen_rtx_TRUNCATE (DImode,
	operand1)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5020 */
rtx
gen_add_losym_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LO_SUM (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5020 */
rtx
gen_add_losym_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5029 */
rtx
gen_ldr_got_small_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_MEM (SImode,
	gen_rtx_LO_SUM (SImode,
	operand1,
	operand2))),
	22));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5029 */
rtx
gen_ldr_got_small_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		gen_rtx_MEM (DImode,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2))),
	22));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5040 */
rtx
gen_ldr_got_small_sidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_MEM (SImode,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2))),
	22)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5052 */
rtx
gen_ldr_got_small_28k_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_MEM (SImode,
	gen_rtx_LO_SUM (SImode,
	operand1,
	operand2))),
	23));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5052 */
rtx
gen_ldr_got_small_28k_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		gen_rtx_MEM (DImode,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2))),
	23));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5063 */
rtx
gen_ldr_got_small_28k_sidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		gen_rtx_MEM (SImode,
	gen_rtx_LO_SUM (DImode,
	operand1,
	operand2))),
	23)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5075 */
rtx
gen_ldr_got_tiny (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	25));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5084 */
rtx
gen_aarch64_load_tp_hard (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	53));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5116 */
rtx
gen_tlsie_small_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	24));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5116 */
rtx
gen_tlsie_small_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	24));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5126 */
rtx
gen_tlsie_small_sidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	24)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5137 */
rtx
gen_tlsie_tiny_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	26));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5137 */
rtx
gen_tlsie_tiny_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	26));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5148 */
rtx
gen_tlsie_tiny_sidi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	26)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5161 */
rtx
gen_tlsle12_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	55));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5161 */
rtx
gen_tlsle12_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	55));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5172 */
rtx
gen_tlsle24_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	56));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5172 */
rtx
gen_tlsle24_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	56));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5183 */
rtx
gen_tlsle32_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5183 */
rtx
gen_tlsle32_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	57));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5193 */
rtx
gen_tlsle48_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	58));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5193 */
rtx
gen_tlsle48_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	58));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5203 */
rtx
gen_tlsdesc_small_si (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (SImode,
	0),
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand0),
	54)),
		gen_hard_reg_clobber (DImode, 30),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5203 */
rtx
gen_tlsdesc_small_di (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (DImode,
	0),
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand0),
	54)),
		gen_hard_reg_clobber (DImode, 30),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5215 */
rtx
gen_stack_tie (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (gen_rtx_MEM (BLKmode,
	gen_rtx_SCRATCH (VOIDmode)),
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand0,
		operand1),
	39));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5228 */
rtx
gen_blockage (void)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		const0_rtx),
	5);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5236 */
rtx
gen_probe_stack_range_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	6));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5236 */
rtx
gen_probe_stack_range_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	6));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5273 */
rtx
gen_stack_protect_set_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	62)),
		gen_rtx_SET (gen_rtx_SCRATCH (SImode),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5273 */
rtx
gen_stack_protect_set_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	62)),
		gen_rtx_SET (gen_rtx_SCRATCH (DImode),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5309 */
rtx
gen_stack_protect_test_si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	63)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5309 */
rtx
gen_stack_protect_test_di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	63)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5321 */
rtx
gen_set_fpcr (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		operand0),
	2);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5328 */
rtx
gen_get_fpcr (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5336 */
rtx
gen_set_fpsr (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
	gen_rtvec (1,
		operand0),
	4);
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5343 */
rtx
gen_get_fpsr (rtx operand0 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:44 */
rtx
gen_aarch64_simd_dupv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:44 */
rtx
gen_aarch64_simd_dupv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:44 */
rtx
gen_aarch64_simd_dupv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:44 */
rtx
gen_aarch64_simd_dupv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:44 */
rtx
gen_aarch64_simd_dupv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:44 */
rtx
gen_aarch64_simd_dupv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:44 */
rtx
gen_aarch64_simd_dupv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:55 */
rtx
gen_aarch64_simd_dupv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:55 */
rtx
gen_aarch64_simd_dupv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:55 */
rtx
gen_aarch64_simd_dupv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:55 */
rtx
gen_aarch64_simd_dupv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:55 */
rtx
gen_aarch64_simd_dupv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:64 */
rtx
gen_aarch64_dup_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_128v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_64v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V16QImode,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_128v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_64v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_128v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_64v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_64v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_128v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_64v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V8HFmode,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_128v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_64v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V4SFmode,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:79 */
rtx
gen_aarch64_dup_lane_to_64v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_DUPLICATE (V2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2)))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:156 */
rtx
gen_load_pairv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:156 */
rtx
gen_load_pairv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:156 */
rtx
gen_load_pairv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:156 */
rtx
gen_load_pairv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:156 */
rtx
gen_load_pairv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_store_pairv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_store_pairv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_store_pairv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_store_pairv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:170 */
rtx
gen_store_pairv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:243 */
rtx
gen_aarch64_simd_mov_from_v16qilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:243 */
rtx
gen_aarch64_simd_mov_from_v8hilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:243 */
rtx
gen_aarch64_simd_mov_from_v4silow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:243 */
rtx
gen_aarch64_simd_mov_from_v2dilow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:243 */
rtx
gen_aarch64_simd_mov_from_v8hflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:243 */
rtx
gen_aarch64_simd_mov_from_v4sflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:243 */
rtx
gen_aarch64_simd_mov_from_v2dflow (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:254 */
rtx
gen_aarch64_simd_mov_from_v16qihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:254 */
rtx
gen_aarch64_simd_mov_from_v8hihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:254 */
rtx
gen_aarch64_simd_mov_from_v4sihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:254 */
rtx
gen_aarch64_simd_mov_from_v2dihigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:254 */
rtx
gen_aarch64_simd_mov_from_v8hfhigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:254 */
rtx
gen_aarch64_simd_mov_from_v4sfhigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:254 */
rtx
gen_aarch64_simd_mov_from_v2dfhigh (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:265 */
rtx
gen_ornv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V8QImode,
	gen_rtx_NOT (V8QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:265 */
rtx
gen_ornv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V16QImode,
	gen_rtx_NOT (V16QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:265 */
rtx
gen_ornv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V4HImode,
	gen_rtx_NOT (V4HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:265 */
rtx
gen_ornv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V8HImode,
	gen_rtx_NOT (V8HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:265 */
rtx
gen_ornv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V2SImode,
	gen_rtx_NOT (V2SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:265 */
rtx
gen_ornv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V4SImode,
	gen_rtx_NOT (V4SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:265 */
rtx
gen_ornv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V2DImode,
	gen_rtx_NOT (V2DImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:274 */
rtx
gen_bicv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V8QImode,
	gen_rtx_NOT (V8QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:274 */
rtx
gen_bicv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V16QImode,
	gen_rtx_NOT (V16QImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:274 */
rtx
gen_bicv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V4HImode,
	gen_rtx_NOT (V4HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:274 */
rtx
gen_bicv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V8HImode,
	gen_rtx_NOT (V8HImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:274 */
rtx
gen_bicv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V2SImode,
	gen_rtx_NOT (V2SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:274 */
rtx
gen_bicv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V4SImode,
	gen_rtx_NOT (V4SImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:274 */
rtx
gen_bicv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V2DImode,
	gen_rtx_NOT (V2DImode,
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:283 */
rtx
gen_addv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:283 */
rtx
gen_addv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:283 */
rtx
gen_addv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:283 */
rtx
gen_addv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:283 */
rtx
gen_addv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:283 */
rtx
gen_addv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:283 */
rtx
gen_addv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:292 */
rtx
gen_subv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:292 */
rtx
gen_subv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:292 */
rtx
gen_subv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:292 */
rtx
gen_subv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:292 */
rtx
gen_subv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:292 */
rtx
gen_subv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:292 */
rtx
gen_subv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:301 */
rtx
gen_mulv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:301 */
rtx
gen_mulv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:301 */
rtx
gen_mulv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:301 */
rtx
gen_mulv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:301 */
rtx
gen_mulv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:301 */
rtx
gen_mulv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:310 */
rtx
gen_bswapv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:310 */
rtx
gen_bswapv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:310 */
rtx
gen_bswapv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:310 */
rtx
gen_bswapv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:310 */
rtx
gen_bswapv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_BSWAP (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:318 */
rtx
gen_aarch64_rbitv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	40));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:318 */
rtx
gen_aarch64_rbitv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	40));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:385 */
rtx
gen_aarch64_rsqrtev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	65));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:385 */
rtx
gen_aarch64_rsqrtev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	65));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:385 */
rtx
gen_aarch64_rsqrtev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	65));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:385 */
rtx
gen_aarch64_rsqrtev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	65));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:385 */
rtx
gen_aarch64_rsqrtev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	65));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:385 */
rtx
gen_aarch64_rsqrtehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	65));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:385 */
rtx
gen_aarch64_rsqrtesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	65));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:385 */
rtx
gen_aarch64_rsqrtedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	65));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_aarch64_rsqrtsv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_aarch64_rsqrtsv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_aarch64_rsqrtsv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_aarch64_rsqrtsv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_aarch64_rsqrtsv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_aarch64_rsqrtshf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_aarch64_rsqrtssf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:393 */
rtx
gen_aarch64_rsqrtsdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	66));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:427 */
rtx
gen_negv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:427 */
rtx
gen_negv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:427 */
rtx
gen_negv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:427 */
rtx
gen_negv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:427 */
rtx
gen_negv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:427 */
rtx
gen_negv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:427 */
rtx
gen_negv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:435 */
rtx
gen_absv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:435 */
rtx
gen_absv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:435 */
rtx
gen_absv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:435 */
rtx
gen_absv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:435 */
rtx
gen_absv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:435 */
rtx
gen_absv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:435 */
rtx
gen_absv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:446 */
rtx
gen_aarch64_absv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	70));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:446 */
rtx
gen_aarch64_absv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	70));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:446 */
rtx
gen_aarch64_absv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	70));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:446 */
rtx
gen_aarch64_absv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	70));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:446 */
rtx
gen_aarch64_absv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	70));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:446 */
rtx
gen_aarch64_absv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	70));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:446 */
rtx
gen_aarch64_absv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	70));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:446 */
rtx
gen_aarch64_absdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	70));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:456 */
rtx
gen_abdv8qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8QImode,
	gen_rtx_MINUS (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:456 */
rtx
gen_abdv16qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V16QImode,
	gen_rtx_MINUS (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:456 */
rtx
gen_abdv4hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4HImode,
	gen_rtx_MINUS (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:456 */
rtx
gen_abdv8hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8HImode,
	gen_rtx_MINUS (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:456 */
rtx
gen_abdv2si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2SImode,
	gen_rtx_MINUS (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:456 */
rtx
gen_abdv4si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4SImode,
	gen_rtx_MINUS (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:466 */
rtx
gen_abav8qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8QImode,
	gen_rtx_ABS (V8QImode,
	gen_rtx_MINUS (V8QImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:466 */
rtx
gen_abav16qi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V16QImode,
	gen_rtx_ABS (V16QImode,
	gen_rtx_MINUS (V16QImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:466 */
rtx
gen_abav4hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HImode,
	gen_rtx_ABS (V4HImode,
	gen_rtx_MINUS (V4HImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:466 */
rtx
gen_abav8hi_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ABS (V8HImode,
	gen_rtx_MINUS (V8HImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:466 */
rtx
gen_abav2si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	gen_rtx_ABS (V2SImode,
	gen_rtx_MINUS (V2SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:466 */
rtx
gen_abav4si_3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ABS (V4SImode,
	gen_rtx_MINUS (V4SImode,
	operand1,
	operand2)),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:477 */
rtx
gen_fabdv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4HFmode,
	gen_rtx_MINUS (V4HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:477 */
rtx
gen_fabdv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8HFmode,
	gen_rtx_MINUS (V8HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:477 */
rtx
gen_fabdv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2SFmode,
	gen_rtx_MINUS (V2SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:477 */
rtx
gen_fabdv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4SFmode,
	gen_rtx_MINUS (V4SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:477 */
rtx
gen_fabdv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2DFmode,
	gen_rtx_MINUS (V2DFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:477 */
rtx
gen_fabdhf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (HFmode,
	gen_rtx_MINUS (HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:477 */
rtx
gen_fabdsf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (SFmode,
	gen_rtx_MINUS (SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:477 */
rtx
gen_fabddf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (DFmode,
	gen_rtx_MINUS (DFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:488 */
rtx
gen_andv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:488 */
rtx
gen_andv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:488 */
rtx
gen_andv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:488 */
rtx
gen_andv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:488 */
rtx
gen_andv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:488 */
rtx
gen_andv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:488 */
rtx
gen_andv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_AND (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:497 */
rtx
gen_iorv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:497 */
rtx
gen_iorv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:497 */
rtx
gen_iorv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:497 */
rtx
gen_iorv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:497 */
rtx
gen_iorv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:497 */
rtx
gen_iorv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:497 */
rtx
gen_iorv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_IOR (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:506 */
rtx
gen_xorv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:506 */
rtx
gen_xorv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:506 */
rtx
gen_xorv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:506 */
rtx
gen_xorv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:506 */
rtx
gen_xorv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:506 */
rtx
gen_xorv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:506 */
rtx
gen_xorv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:515 */
rtx
gen_one_cmplv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:515 */
rtx
gen_one_cmplv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:515 */
rtx
gen_one_cmplv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:515 */
rtx
gen_one_cmplv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:515 */
rtx
gen_one_cmplv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:515 */
rtx
gen_one_cmplv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:515 */
rtx
gen_one_cmplv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NOT (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:523 */
rtx
gen_aarch64_simd_vec_setv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V8QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:523 */
rtx
gen_aarch64_simd_vec_setv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V16QImode,
	gen_rtx_VEC_DUPLICATE (V16QImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:523 */
rtx
gen_aarch64_simd_vec_setv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V4HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:523 */
rtx
gen_aarch64_simd_vec_setv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V8HImode,
	gen_rtx_VEC_DUPLICATE (V8HImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:523 */
rtx
gen_aarch64_simd_vec_setv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V2SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:523 */
rtx
gen_aarch64_simd_vec_setv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4SImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:592 */
rtx
gen_aarch64_simd_lshrv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:592 */
rtx
gen_aarch64_simd_lshrv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:592 */
rtx
gen_aarch64_simd_lshrv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:592 */
rtx
gen_aarch64_simd_lshrv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:592 */
rtx
gen_aarch64_simd_lshrv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:592 */
rtx
gen_aarch64_simd_lshrv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:592 */
rtx
gen_aarch64_simd_lshrv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:601 */
rtx
gen_aarch64_simd_ashrv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:601 */
rtx
gen_aarch64_simd_ashrv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:601 */
rtx
gen_aarch64_simd_ashrv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:601 */
rtx
gen_aarch64_simd_ashrv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:601 */
rtx
gen_aarch64_simd_ashrv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:601 */
rtx
gen_aarch64_simd_ashrv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:601 */
rtx
gen_aarch64_simd_ashrv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:610 */
rtx
gen_aarch64_simd_imm_shlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:610 */
rtx
gen_aarch64_simd_imm_shlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:610 */
rtx
gen_aarch64_simd_imm_shlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:610 */
rtx
gen_aarch64_simd_imm_shlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:610 */
rtx
gen_aarch64_simd_imm_shlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:610 */
rtx
gen_aarch64_simd_imm_shlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:610 */
rtx
gen_aarch64_simd_imm_shlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:619 */
rtx
gen_aarch64_simd_reg_sshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:619 */
rtx
gen_aarch64_simd_reg_sshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:619 */
rtx
gen_aarch64_simd_reg_sshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:619 */
rtx
gen_aarch64_simd_reg_sshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:619 */
rtx
gen_aarch64_simd_reg_sshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:619 */
rtx
gen_aarch64_simd_reg_sshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:619 */
rtx
gen_aarch64_simd_reg_sshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:628 */
rtx
gen_aarch64_simd_reg_shlv8qi_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	69));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:628 */
rtx
gen_aarch64_simd_reg_shlv16qi_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	69));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:628 */
rtx
gen_aarch64_simd_reg_shlv4hi_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	69));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:628 */
rtx
gen_aarch64_simd_reg_shlv8hi_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	69));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:628 */
rtx
gen_aarch64_simd_reg_shlv2si_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	69));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:628 */
rtx
gen_aarch64_simd_reg_shlv4si_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	69));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:628 */
rtx
gen_aarch64_simd_reg_shlv2di_unsigned (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	69));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:638 */
rtx
gen_aarch64_simd_reg_shlv8qi_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	68));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:638 */
rtx
gen_aarch64_simd_reg_shlv16qi_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	68));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:638 */
rtx
gen_aarch64_simd_reg_shlv4hi_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	68));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:638 */
rtx
gen_aarch64_simd_reg_shlv8hi_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	68));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:638 */
rtx
gen_aarch64_simd_reg_shlv2si_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	68));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:638 */
rtx
gen_aarch64_simd_reg_shlv4si_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	68));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:638 */
rtx
gen_aarch64_simd_reg_shlv2di_signed (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	68));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:874 */
rtx
gen_vec_shr_v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:874 */
rtx
gen_vec_shr_v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:874 */
rtx
gen_vec_shr_v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:874 */
rtx
gen_vec_shr_v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:874 */
rtx
gen_vec_shr_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	166));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:889 */
rtx
gen_aarch64_simd_vec_setv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2DImode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:926 */
rtx
gen_aarch64_simd_vec_setv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V4HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:926 */
rtx
gen_aarch64_simd_vec_setv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V8HFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:926 */
rtx
gen_aarch64_simd_vec_setv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V2SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:926 */
rtx
gen_aarch64_simd_vec_setv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V4SFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:926 */
rtx
gen_aarch64_simd_vec_setv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_MERGE (V2DFmode,
	gen_rtx_VEC_DUPLICATE (V2DFmode,
	operand1),
	operand3,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:957 */
rtx
gen_aarch64_mlav8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8QImode,
	gen_rtx_MULT (V8QImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:957 */
rtx
gen_aarch64_mlav16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V16QImode,
	gen_rtx_MULT (V16QImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:957 */
rtx
gen_aarch64_mlav4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HImode,
	gen_rtx_MULT (V4HImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:957 */
rtx
gen_aarch64_mlav8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_MULT (V8HImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:957 */
rtx
gen_aarch64_mlav2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	gen_rtx_MULT (V2SImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:957 */
rtx
gen_aarch64_mlav4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_MULT (V4SImode,
	operand2,
	operand3),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1005 */
rtx
gen_aarch64_mlsv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8QImode,
	operand1,
	gen_rtx_MULT (V8QImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1005 */
rtx
gen_aarch64_mlsv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V16QImode,
	operand1,
	gen_rtx_MULT (V16QImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1005 */
rtx
gen_aarch64_mlsv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4HImode,
	operand1,
	gen_rtx_MULT (V4HImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1005 */
rtx
gen_aarch64_mlsv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_MULT (V8HImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1005 */
rtx
gen_aarch64_mlsv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2SImode,
	operand1,
	gen_rtx_MULT (V2SImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1005 */
rtx
gen_aarch64_mlsv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_MULT (V4SImode,
	operand2,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_smaxv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_sminv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_umaxv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_uminv8qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_smaxv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_sminv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_umaxv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_uminv16qi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_smaxv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_sminv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_umaxv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_uminv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_smaxv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_sminv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_umaxv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_uminv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_smaxv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_sminv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_umaxv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_uminv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_smaxv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_sminv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_umaxv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMAX (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1053 */
rtx
gen_uminv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UMIN (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_umaxpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_uminpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_smaxpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_sminpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_umaxpv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_uminpv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_smaxpv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_sminpv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_umaxpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_uminpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_smaxpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_sminpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_umaxpv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_uminpv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_smaxpv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_sminpv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_umaxpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_uminpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_smaxpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_sminpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_umaxpv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_uminpv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_smaxpv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1096 */
rtx
gen_aarch64_sminpv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smax_nanpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smin_nanpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smaxpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_sminpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smax_nanpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smin_nanpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smaxpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_sminpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smax_nanpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smin_nanpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smaxpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_sminpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smax_nanpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smin_nanpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smaxpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_sminpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smax_nanpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smin_nanpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_smaxpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1107 */
rtx
gen_aarch64_sminpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1127 */
rtx
gen_move_lo_quad_internal_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1127 */
rtx
gen_move_lo_quad_internal_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1127 */
rtx
gen_move_lo_quad_internal_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1127 */
rtx
gen_move_lo_quad_internal_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1127 */
rtx
gen_move_lo_quad_internal_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1143 */
rtx
gen_move_lo_quad_internal_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	operand1,
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1143 */
rtx
gen_move_lo_quad_internal_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	operand1,
	const0_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1159 */
rtx
gen_move_lo_quad_internal_be_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1159 */
rtx
gen_move_lo_quad_internal_be_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1159 */
rtx
gen_move_lo_quad_internal_be_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1159 */
rtx
gen_move_lo_quad_internal_be_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1159 */
rtx
gen_move_lo_quad_internal_be_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1175 */
rtx
gen_move_lo_quad_internal_be_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1175 */
rtx
gen_move_lo_quad_internal_be_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1209 */
rtx
gen_aarch64_simd_move_hi_quad_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1209 */
rtx
gen_aarch64_simd_move_hi_quad_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1209 */
rtx
gen_aarch64_simd_move_hi_quad_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1209 */
rtx
gen_aarch64_simd_move_hi_quad_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_VEC_SELECT (DImode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1209 */
rtx
gen_aarch64_simd_move_hi_quad_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1209 */
rtx
gen_aarch64_simd_move_hi_quad_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1209 */
rtx
gen_aarch64_simd_move_hi_quad_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_VEC_SELECT (DFmode,
	operand0,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1223 */
rtx
gen_aarch64_simd_move_hi_quad_be_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	operand1,
	gen_rtx_VEC_SELECT (V8QImode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1223 */
rtx
gen_aarch64_simd_move_hi_quad_be_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	operand1,
	gen_rtx_VEC_SELECT (V4HImode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1223 */
rtx
gen_aarch64_simd_move_hi_quad_be_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	operand1,
	gen_rtx_VEC_SELECT (V2SImode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1223 */
rtx
gen_aarch64_simd_move_hi_quad_be_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	operand1,
	gen_rtx_VEC_SELECT (DImode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1223 */
rtx
gen_aarch64_simd_move_hi_quad_be_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1223 */
rtx
gen_aarch64_simd_move_hi_quad_be_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1223 */
rtx
gen_aarch64_simd_move_hi_quad_be_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	operand1,
	gen_rtx_VEC_SELECT (DFmode,
	operand0,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1255 */
rtx
gen_aarch64_simd_vec_pack_trunc_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1255 */
rtx
gen_aarch64_simd_vec_pack_trunc_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1255 */
rtx
gen_aarch64_simd_vec_pack_trunc_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_TRUNCATE (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1281 */
rtx
gen_vec_pack_trunc_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_TRUNCATE (V8QImode,
	operand1),
	gen_rtx_TRUNCATE (V8QImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1281 */
rtx
gen_vec_pack_trunc_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_TRUNCATE (V4HImode,
	operand1),
	gen_rtx_TRUNCATE (V4HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1281 */
rtx
gen_vec_pack_trunc_v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_TRUNCATE (V2SImode,
	operand1),
	gen_rtx_TRUNCATE (V2SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1299 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1299 */
rtx
gen_aarch64_simd_vec_unpacku_lo_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1299 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1299 */
rtx
gen_aarch64_simd_vec_unpacku_lo_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1299 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1299 */
rtx
gen_aarch64_simd_vec_unpacku_lo_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1310 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1310 */
rtx
gen_aarch64_simd_vec_unpacku_hi_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1310 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1310 */
rtx
gen_aarch64_simd_vec_unpacku_hi_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1310 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1310 */
rtx
gen_aarch64_simd_vec_unpacku_hi_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1439 */
rtx
gen_aarch64_simd_vec_smult_lo_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1439 */
rtx
gen_aarch64_simd_vec_umult_lo_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1439 */
rtx
gen_aarch64_simd_vec_smult_lo_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1439 */
rtx
gen_aarch64_simd_vec_umult_lo_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1439 */
rtx
gen_aarch64_simd_vec_smult_lo_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1439 */
rtx
gen_aarch64_simd_vec_umult_lo_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1466 */
rtx
gen_aarch64_simd_vec_smult_hi_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1466 */
rtx
gen_aarch64_simd_vec_umult_hi_v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1466 */
rtx
gen_aarch64_simd_vec_smult_hi_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1466 */
rtx
gen_aarch64_simd_vec_umult_hi_v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1466 */
rtx
gen_aarch64_simd_vec_smult_hi_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1466 */
rtx
gen_aarch64_simd_vec_umult_hi_v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1519 */
rtx
gen_addv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1519 */
rtx
gen_addv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1519 */
rtx
gen_addv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1519 */
rtx
gen_addv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1519 */
rtx
gen_addv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1528 */
rtx
gen_subv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1528 */
rtx
gen_subv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1528 */
rtx
gen_subv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1528 */
rtx
gen_subv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1528 */
rtx
gen_subv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1537 */
rtx
gen_mulv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1537 */
rtx
gen_mulv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1537 */
rtx
gen_mulv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1537 */
rtx
gen_mulv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1537 */
rtx
gen_mulv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MULT (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1567 */
rtx
gen_negv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1567 */
rtx
gen_negv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1567 */
rtx
gen_negv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1567 */
rtx
gen_negv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1567 */
rtx
gen_negv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1575 */
rtx
gen_absv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1575 */
rtx
gen_absv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1575 */
rtx
gen_absv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1575 */
rtx
gen_absv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1575 */
rtx
gen_absv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ABS (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1583 */
rtx
gen_fmav4hf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4HFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1583 */
rtx
gen_fmav8hf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V8HFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1583 */
rtx
gen_fmav2sf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1583 */
rtx
gen_fmav4sf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1583 */
rtx
gen_fmav2df4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2DFmode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1656 */
rtx
gen_fnmav4hf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4HFmode,
	operand1,
	gen_rtx_NEG (V4HFmode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1656 */
rtx
gen_fnmav8hf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V8HFmode,
	operand1,
	gen_rtx_NEG (V8HFmode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1656 */
rtx
gen_fnmav2sf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2SFmode,
	operand1,
	gen_rtx_NEG (V2SFmode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1656 */
rtx
gen_fnmav4sf4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V4SFmode,
	operand1,
	gen_rtx_NEG (V4SFmode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1656 */
rtx
gen_fnmav2df4 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FMA (V2DFmode,
	operand1,
	gen_rtx_NEG (V2DFmode,
	operand2),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_btruncv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_ceilv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_floorv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_frintnv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_nearbyintv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_rintv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_roundv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	15));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_btruncv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_ceilv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_floorv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_frintnv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_nearbyintv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_rintv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_roundv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	15));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_btruncv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_ceilv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_floorv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_frintnv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_nearbyintv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_rintv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_roundv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	15));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_btruncv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_ceilv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_floorv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_frintnv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_nearbyintv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_rintv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_roundv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	15));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_btruncv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	21));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_ceilv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	19));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_floorv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	17));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_frintnv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	18));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_nearbyintv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	16));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_rintv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	20));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1737 */
rtx
gen_roundv2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	15));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceilv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfloorv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lroundv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncuv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceiluv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lflooruv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lrounduv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnuv4hfv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceilv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfloorv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lroundv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncuv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceiluv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lflooruv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lrounduv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnuv8hfv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceilv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfloorv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lroundv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncuv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceiluv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lflooruv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lrounduv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnuv2sfv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceilv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfloorv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lroundv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncuv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceiluv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lflooruv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lrounduv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnuv4sfv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceilv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfloorv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lroundv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lbtruncuv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lceiluv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lflooruv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lrounduv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1748 */
rtx
gen_lfrintnuv2dfv2di2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lbtrunchfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lceilhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lfloorhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lroundhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lfrintnhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lbtruncuhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	21)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lceiluhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	19)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lflooruhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	17)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lrounduhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	15)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1759 */
rtx
gen_lfrintnuhfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	18)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1768 */
rtx
gen_fix_trunchfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FIX (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1768 */
rtx
gen_fixuns_trunchfhi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1776 */
rtx
gen_floathihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1776 */
rtx
gen_floatunshihf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatv4hiv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatunsv4hiv4hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatv8hiv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatunsv8hiv8hf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V8HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatv2siv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatunsv2siv2sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatv4siv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatunsv4siv4sf2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatv2div2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1827 */
rtx
gen_floatunsv2div2df2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FLOAT (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1842 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1842 */
rtx
gen_aarch64_simd_vec_unpacks_lo_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V2DFmode,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzsv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzuv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzsv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzuv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzsv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzuv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzsv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzuv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzsv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1855 */
rtx
gen_fcvtzuv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_scvtfv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_ucvtfv4hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_scvtfv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_ucvtfv8hi3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_scvtfv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_ucvtfv2si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_scvtfv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_ucvtfv4si3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_scvtfv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	41));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1866 */
rtx
gen_ucvtfv2di3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	59));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1898 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	gen_rtx_VEC_SELECT (V4HFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1898 */
rtx
gen_aarch64_simd_vec_unpacks_hi_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V2DFmode,
	gen_rtx_VEC_SELECT (V2SFmode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1920 */
rtx
gen_aarch64_float_extend_lo_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V2DFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1920 */
rtx
gen_aarch64_float_extend_lo_v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_EXTEND (V4SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1931 */
rtx
gen_aarch64_float_truncate_lo_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1931 */
rtx
gen_aarch64_float_truncate_lo_v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_FLOAT_TRUNCATE (V4HFmode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1940 */
rtx
gen_aarch64_float_truncate_hi_v4sf_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1940 */
rtx
gen_aarch64_float_truncate_hi_v8hf_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	gen_rtx_FLOAT_TRUNCATE (V4HFmode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1951 */
rtx
gen_aarch64_float_truncate_hi_v4sf_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1951 */
rtx
gen_aarch64_float_truncate_hi_v8hf_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_FLOAT_TRUNCATE (V4HFmode,
	operand2),
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_smaxv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_sminv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V4HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_smaxv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_sminv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_smaxv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_sminv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V2SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_smaxv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_sminv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_smaxv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMAX (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2032 */
rtx
gen_sminv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SMIN (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smax_nanv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smin_nanv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	74));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fmaxv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	169));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fminv4hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	170));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smax_nanv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smin_nanv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	74));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fmaxv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	169));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fminv8hf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	170));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smax_nanv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smin_nanv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	74));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fmaxv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	169));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fminv2sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	170));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smax_nanv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smin_nanv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	74));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fmaxv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	169));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fminv4sf3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	170));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smax_nanv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	71));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_smin_nanv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	74));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fmaxv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	169));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2044 */
rtx
gen_fminv2df3 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	170));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2070 */
rtx
gen_aarch64_faddpv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	77));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2070 */
rtx
gen_aarch64_faddpv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	77));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2070 */
rtx
gen_aarch64_faddpv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	77));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2070 */
rtx
gen_aarch64_faddpv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	77));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2070 */
rtx
gen_aarch64_faddpv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	77));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2080 */
rtx
gen_aarch64_reduc_plus_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	78));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2080 */
rtx
gen_aarch64_reduc_plus_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	78));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2080 */
rtx
gen_aarch64_reduc_plus_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	78));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2080 */
rtx
gen_aarch64_reduc_plus_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	78));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2080 */
rtx
gen_aarch64_reduc_plus_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	78));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2080 */
rtx
gen_aarch64_reduc_plus_internalv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	78));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2089 */
rtx
gen_aarch64_reduc_plus_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	78));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_reduc_plus_scal_v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	77));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2098 */
rtx
gen_reduc_plus_scal_v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	77));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_clrsbv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_clrsbv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_clrsbv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_clrsbv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_clrsbv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2121 */
rtx
gen_clrsbv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLRSB (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2129 */
rtx
gen_clzv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2129 */
rtx
gen_clzv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2129 */
rtx
gen_clzv4hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2129 */
rtx
gen_clzv8hi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2129 */
rtx
gen_clzv2si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2129 */
rtx
gen_clzv4si2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_CLZ (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2137 */
rtx
gen_popcountv8qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2137 */
rtx
gen_popcountv16qi2 (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_POPCOUNT (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umax_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umin_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smax_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smin_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umax_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umin_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smax_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smin_internalv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umax_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umin_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smax_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smin_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umax_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umin_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smax_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smin_internalv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umax_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_umin_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smax_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2180 */
rtx
gen_aarch64_reduc_smin_internalv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2189 */
rtx
gen_aarch64_reduc_umax_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	81));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2189 */
rtx
gen_aarch64_reduc_umin_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	82));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2189 */
rtx
gen_aarch64_reduc_smax_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	79));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2189 */
rtx
gen_aarch64_reduc_smin_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	80));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_nan_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_nan_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_nan_internalv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_nan_internalv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_internalv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_internalv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_nan_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_nan_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_nan_internalv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_nan_internalv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_internalv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_internalv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_nan_internalv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	73));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_nan_internalv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	76));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smax_internalv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	72));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2198 */
rtx
gen_aarch64_reduc_smin_internalv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	75));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2227 */
rtx
gen_aarch64_simd_bslv8qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8QImode,
	gen_rtx_AND (V8QImode,
	gen_rtx_XOR (V8QImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2227 */
rtx
gen_aarch64_simd_bslv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V16QImode,
	gen_rtx_AND (V16QImode,
	gen_rtx_XOR (V16QImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2227 */
rtx
gen_aarch64_simd_bslv4hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4HImode,
	gen_rtx_AND (V4HImode,
	gen_rtx_XOR (V4HImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2227 */
rtx
gen_aarch64_simd_bslv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V8HImode,
	gen_rtx_AND (V8HImode,
	gen_rtx_XOR (V8HImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2227 */
rtx
gen_aarch64_simd_bslv2si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2SImode,
	gen_rtx_AND (V2SImode,
	gen_rtx_XOR (V2SImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2227 */
rtx
gen_aarch64_simd_bslv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V4SImode,
	gen_rtx_AND (V4SImode,
	gen_rtx_XOR (V4SImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2227 */
rtx
gen_aarch64_simd_bslv2di_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (V2DImode,
	gen_rtx_AND (V2DImode,
	gen_rtx_XOR (V2DImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2227 */
rtx
gen_aarch64_simd_bsldi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	gen_rtx_AND (DImode,
	gen_rtx_XOR (DImode,
	operand3,
	operand2),
	operand1),
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (QImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DImode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (HFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (SFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2685 */
rtx
gen_aarch64_get_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_SELECT (DFmode,
	operand1,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
rtx
gen_aarch64_combine_internalv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
rtx
gen_aarch64_combine_internalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
rtx
gen_aarch64_combine_internalv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V8HFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
rtx
gen_aarch64_combine_internalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
rtx
gen_aarch64_combine_internalv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
rtx
gen_aarch64_combine_internaldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
rtx
gen_aarch64_combine_internaldf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2DFmode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_saddlv16qi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_ssublv16qi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_uaddlv16qi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_usublv16qi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_saddlv8hi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_ssublv8hi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_uaddlv8hi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_usublv8hi_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_saddlv4si_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_ssublv4si_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_uaddlv4si_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2796 */
rtx
gen_aarch64_usublv4si_hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_saddlv16qi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_ssublv16qi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_uaddlv16qi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_usublv16qi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_saddlv8hi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_ssublv8hi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_uaddlv8hi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_usublv8hi_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_saddlv4si_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_ssublv4si_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_uaddlv4si_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2809 */
rtx
gen_aarch64_usublv4si_lo_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_saddlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_ssublv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_uaddlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_usublv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_saddlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_ssublv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_uaddlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_usublv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_saddlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_ssublv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_uaddlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2871 */
rtx
gen_aarch64_usublv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand1),
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_saddwv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_ssubwv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_uaddwv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_usubwv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_saddwv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_ssubwv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_uaddwv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_usubwv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_saddwv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_ssubwv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_uaddwv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2940 */
rtx
gen_aarch64_usubwv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_saddwv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_ssubwv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_uaddwv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_usubwv16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_saddwv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_ssubwv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_uaddwv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_usubwv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_saddwv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_ssubwv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_uaddwv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2950 */
rtx
gen_aarch64_usubwv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_saddw2v16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_ssubw2v16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_uaddw2v16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_usubw2v16qi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V8HImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V8HImode,
	gen_rtx_VEC_SELECT (V8QImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_saddw2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_ssubw2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_uaddw2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_usubw2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V4SImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_saddw2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_ssubw2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_uaddw2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2962 */
rtx
gen_aarch64_usubw2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (V2DImode,
	operand1,
	gen_rtx_ZERO_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	83));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	84));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	85));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	86));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	87));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	88));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	90));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	83));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	84));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	85));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	86));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	87));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	88));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	90));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	83));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	84));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	85));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	86));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	87));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	88));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	90));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	83));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	84));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	85));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	86));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	87));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	88));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	90));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	83));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	84));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	85));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	86));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	87));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	88));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	90));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	83));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	84));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	85));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	86));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_shsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	87));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_uhsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	88));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_srhsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	89));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3025 */
rtx
gen_aarch64_urhsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	90));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_addhnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	91));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_raddhnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	92));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_subhnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	93));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_rsubhnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	94));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_addhnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	91));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_raddhnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	92));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_subhnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	93));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_rsubhnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	94));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_addhnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	91));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_raddhnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	92));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_subhnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	93));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3037 */
rtx
gen_aarch64_rsubhnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	94));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_addhn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	95));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_raddhn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	96));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_subhn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	97));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_rsubhn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	98));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_addhn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	95));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_raddhn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	96));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_subhn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	97));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_rsubhn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	98));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_addhn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	95));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_raddhn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	96));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_subhn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	97));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3047 */
rtx
gen_aarch64_rsubhn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	98));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3060 */
rtx
gen_aarch64_pmulv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	101));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3060 */
rtx
gen_aarch64_pmulv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	101));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3072 */
rtx
gen_aarch64_fmulxv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	102));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3072 */
rtx
gen_aarch64_fmulxv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	102));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3072 */
rtx
gen_aarch64_fmulxv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	102));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3072 */
rtx
gen_aarch64_fmulxv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	102));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3072 */
rtx
gen_aarch64_fmulxv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	102));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3072 */
rtx
gen_aarch64_fmulxhf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	102));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3072 */
rtx
gen_aarch64_fmulxsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	102));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3072 */
rtx
gen_aarch64_fmulxdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	102));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V8QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V16QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V4HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V8HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V2SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V4SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (V2DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (QImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (HImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (SImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_PLUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_sqsubdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3157 */
rtx
gen_aarch64_uqsubdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_US_MINUS (DImode,
	operand1,
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_suqadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	104));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3168 */
rtx
gen_aarch64_usqadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	103));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3180 */
rtx
gen_aarch64_sqmovunv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	105));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3180 */
rtx
gen_aarch64_sqmovunv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	105));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3180 */
rtx
gen_aarch64_sqmovunv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	105));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3180 */
rtx
gen_aarch64_sqmovunhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand1),
	105));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3180 */
rtx
gen_aarch64_sqmovunsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (1,
		operand1),
	105));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3180 */
rtx
gen_aarch64_sqmovundi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	105));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_sqmovnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	106));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_uqmovnv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	107));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_sqmovnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	106));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_uqmovnv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	107));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_sqmovnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	106));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_uqmovnv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	107));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_sqmovnhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand1),
	106));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_uqmovnhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand1),
	107));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_sqmovnsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (1,
		operand1),
	106));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_uqmovnsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (1,
		operand1),
	107));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_sqmovndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	106));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3191 */
rtx
gen_aarch64_uqmovndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	107));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V8QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V16QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V4HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V8HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V2SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V4SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (V2DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (QImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqneghi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabshi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabssi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqnegdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_NEG (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3202 */
rtx
gen_aarch64_sqabsdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ABS (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqdmulhv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqrdmulhv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqdmulhv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqrdmulhv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqdmulhv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqrdmulhv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqdmulhv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqrdmulhv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqdmulhhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqrdmulhhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqdmulhsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3213 */
rtx
gen_aarch64_sqrdmulhsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_sqdmulh_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_sqrdmulh_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_sqdmulh_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_sqrdmulh_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_sqdmulh_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_sqrdmulh_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_sqdmulh_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3226 */
rtx
gen_aarch64_sqrdmulh_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_sqdmulh_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_sqrdmulh_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_sqdmulh_laneqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_sqrdmulh_laneqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_sqdmulh_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_sqrdmulh_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_sqdmulh_laneqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3241 */
rtx
gen_aarch64_sqrdmulh_laneqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3256 */
rtx
gen_aarch64_sqdmulh_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3256 */
rtx
gen_aarch64_sqrdmulh_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3256 */
rtx
gen_aarch64_sqdmulh_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3256 */
rtx
gen_aarch64_sqrdmulh_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3271 */
rtx
gen_aarch64_sqdmulh_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3271 */
rtx
gen_aarch64_sqrdmulh_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3271 */
rtx
gen_aarch64_sqdmulh_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	99));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3271 */
rtx
gen_aarch64_sqrdmulh_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))),
	100));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlahv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlshv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlahv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlshv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlahv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlshv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlahv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlshv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlahhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlshhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlahsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3288 */
rtx
gen_aarch64_sqrdmlshsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3302 */
rtx
gen_aarch64_sqrdmlah_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3302 */
rtx
gen_aarch64_sqrdmlsh_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3302 */
rtx
gen_aarch64_sqrdmlah_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3302 */
rtx
gen_aarch64_sqrdmlsh_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3302 */
rtx
gen_aarch64_sqrdmlah_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3302 */
rtx
gen_aarch64_sqrdmlsh_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3302 */
rtx
gen_aarch64_sqrdmlah_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3302 */
rtx
gen_aarch64_sqrdmlsh_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3320 */
rtx
gen_aarch64_sqrdmlah_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3320 */
rtx
gen_aarch64_sqrdmlsh_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3320 */
rtx
gen_aarch64_sqrdmlah_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3320 */
rtx
gen_aarch64_sqrdmlsh_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3340 */
rtx
gen_aarch64_sqrdmlah_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3340 */
rtx
gen_aarch64_sqrdmlsh_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3340 */
rtx
gen_aarch64_sqrdmlah_laneqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3340 */
rtx
gen_aarch64_sqrdmlsh_laneqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3340 */
rtx
gen_aarch64_sqrdmlah_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3340 */
rtx
gen_aarch64_sqrdmlsh_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3340 */
rtx
gen_aarch64_sqrdmlah_laneqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3340 */
rtx
gen_aarch64_sqrdmlsh_laneqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3358 */
rtx
gen_aarch64_sqrdmlah_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3358 */
rtx
gen_aarch64_sqrdmlsh_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3358 */
rtx
gen_aarch64_sqrdmlah_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	167));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3358 */
rtx
gen_aarch64_sqrdmlsh_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))),
	168));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3378 */
rtx
gen_aarch64_sqdmlalv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3378 */
rtx
gen_aarch64_sqdmlslv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3378 */
rtx
gen_aarch64_sqdmlalv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3378 */
rtx
gen_aarch64_sqdmlslv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3378 */
rtx
gen_aarch64_sqdmlalhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3378 */
rtx
gen_aarch64_sqdmlslhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3378 */
rtx
gen_aarch64_sqdmlalsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3378 */
rtx
gen_aarch64_sqdmlslsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	operand3)),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3396 */
rtx
gen_aarch64_sqdmlal_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3396 */
rtx
gen_aarch64_sqdmlsl_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3396 */
rtx
gen_aarch64_sqdmlal_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3396 */
rtx
gen_aarch64_sqdmlsl_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3420 */
rtx
gen_aarch64_sqdmlal_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3420 */
rtx
gen_aarch64_sqdmlsl_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3420 */
rtx
gen_aarch64_sqdmlal_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3420 */
rtx
gen_aarch64_sqdmlsl_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3444 */
rtx
gen_aarch64_sqdmlal_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3444 */
rtx
gen_aarch64_sqdmlsl_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3444 */
rtx
gen_aarch64_sqdmlal_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3444 */
rtx
gen_aarch64_sqdmlsl_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3467 */
rtx
gen_aarch64_sqdmlal_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3467 */
rtx
gen_aarch64_sqdmlsl_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (SImode,
	operand1,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3467 */
rtx
gen_aarch64_sqdmlal_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3467 */
rtx
gen_aarch64_sqdmlsl_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (DImode,
	operand1,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3492 */
rtx
gen_aarch64_sqdmlal_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3492 */
rtx
gen_aarch64_sqdmlsl_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3492 */
rtx
gen_aarch64_sqdmlal_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3492 */
rtx
gen_aarch64_sqdmlsl_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3511 */
rtx
gen_aarch64_sqdmlal2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand3,
	operand4))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3511 */
rtx
gen_aarch64_sqdmlsl2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand3,
	operand4))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3511 */
rtx
gen_aarch64_sqdmlal2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand3,
	operand4))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3511 */
rtx
gen_aarch64_sqdmlsl2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand3,
	operand4))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3559 */
rtx
gen_aarch64_sqdmlal2_lanev8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3559 */
rtx
gen_aarch64_sqdmlsl2_lanev8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3559 */
rtx
gen_aarch64_sqdmlal2_lanev4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3559 */
rtx
gen_aarch64_sqdmlsl2_lanev4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3585 */
rtx
gen_aarch64_sqdmlal2_laneqv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3585 */
rtx
gen_aarch64_sqdmlsl2_laneqv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3585 */
rtx
gen_aarch64_sqdmlal2_laneqv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3585 */
rtx
gen_aarch64_sqdmlsl2_laneqv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand5)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand3,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand4)))))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3671 */
rtx
gen_aarch64_sqdmlal2_nv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3671 */
rtx
gen_aarch64_sqdmlsl2_nv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V4SImode,
	operand1,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3671 */
rtx
gen_aarch64_sqdmlal2_nv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_PLUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3671 */
rtx
gen_aarch64_sqdmlsl2_nv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_MINUS (V2DImode,
	operand1,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand3))),
	const1_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3720 */
rtx
gen_aarch64_sqdmullv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand2)),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3720 */
rtx
gen_aarch64_sqdmullv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand2)),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3720 */
rtx
gen_aarch64_sqdmullhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (SImode,
	operand2)),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3720 */
rtx
gen_aarch64_sqdmullsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	operand2)),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3736 */
rtx
gen_aarch64_sqdmull_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3736 */
rtx
gen_aarch64_sqdmull_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3757 */
rtx
gen_aarch64_sqdmull_laneqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3757 */
rtx
gen_aarch64_sqdmull_laneqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3778 */
rtx
gen_aarch64_sqdmull_lanehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3778 */
rtx
gen_aarch64_sqdmull_lanesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqdmull_laneqhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (SImode,
	gen_rtx_MULT (SImode,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (SImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3798 */
rtx
gen_aarch64_sqdmull_laneqsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (DImode,
	gen_rtx_MULT (DImode,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (DImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3820 */
rtx
gen_aarch64_sqdmull_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand2))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3820 */
rtx
gen_aarch64_sqdmull_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand2))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3840 */
rtx
gen_aarch64_sqdmull2v8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand2,
	operand3))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3840 */
rtx
gen_aarch64_sqdmull2v4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand2,
	operand3))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3873 */
rtx
gen_aarch64_sqdmull2_lanev8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3873 */
rtx
gen_aarch64_sqdmull2_lanev4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3896 */
rtx
gen_aarch64_sqdmull2_laneqv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand4)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	gen_rtx_VEC_SELECT (HImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3896 */
rtx
gen_aarch64_sqdmull2_laneqv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand4)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	gen_rtx_VEC_SELECT (SImode,
	operand2,
	gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (1,
		operand3)))))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3949 */
rtx
gen_aarch64_sqdmull2_nv8hi_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V4SImode,
	gen_rtx_MULT (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_SELECT (V4HImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V4SImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	operand2))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3949 */
rtx
gen_aarch64_sqdmull2_nv4si_internal (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SS_ASHIFT (V2DImode,
	gen_rtx_MULT (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_SELECT (V2SImode,
	operand1,
	operand3)),
	gen_rtx_SIGN_EXTEND (V2DImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	operand2))),
	const1_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_sshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_ushlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_srshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_urshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_sshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_ushlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_srshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_urshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_sshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_ushlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_srshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_urshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_sshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_ushlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_srshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_urshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_sshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_ushlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_srshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_urshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_sshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_ushlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_srshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_urshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_sshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_ushlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_srshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_urshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_sshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	123));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_ushldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	124));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_srshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	125));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3981 */
rtx
gen_aarch64_urshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	126));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshlsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_sqrshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	127));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3995 */
rtx
gen_aarch64_uqrshldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	128));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4008 */
rtx
gen_aarch64_sshll_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	133));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4008 */
rtx
gen_aarch64_ushll_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	134));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4008 */
rtx
gen_aarch64_sshll_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	133));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4008 */
rtx
gen_aarch64_ushll_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	134));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4008 */
rtx
gen_aarch64_sshll_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	133));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4008 */
rtx
gen_aarch64_ushll_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	134));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4026 */
rtx
gen_aarch64_sshll2_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	133));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4026 */
rtx
gen_aarch64_ushll2_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	134));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4026 */
rtx
gen_aarch64_sshll2_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	133));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4026 */
rtx
gen_aarch64_ushll2_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	134));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4026 */
rtx
gen_aarch64_sshll2_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	133));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4026 */
rtx
gen_aarch64_ushll2_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	134));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_srshr_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_urshr_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_srshr_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_urshr_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_srshr_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_urshr_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_srshr_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_urshr_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_srshr_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_urshr_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_srshr_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_urshr_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_srshr_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_urshr_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_srshr_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	112));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4043 */
rtx
gen_aarch64_urshr_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	113));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ssra_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	108));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_usra_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	109));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_srsra_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	110));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ursra_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	111));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ssra_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	108));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_usra_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	109));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_srsra_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	110));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ursra_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	111));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ssra_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	108));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_usra_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	109));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_srsra_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	110));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ursra_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	111));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ssra_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	108));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_usra_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	109));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_srsra_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	110));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ursra_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	111));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ssra_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	108));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_usra_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	109));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_srsra_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	110));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ursra_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	111));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ssra_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	108));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_usra_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	109));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_srsra_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	110));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ursra_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	111));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ssra_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	108));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_usra_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	109));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_srsra_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	110));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ursra_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	111));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ssra_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	108));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_usra_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	109));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_srsra_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	110));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4056 */
rtx
gen_aarch64_ursra_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	111));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssli_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	129));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usli_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	130));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssri_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	131));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usri_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	132));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssli_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	129));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usli_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	130));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssri_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	131));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usri_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	132));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssli_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	129));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usli_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	130));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssri_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	131));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usri_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	132));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssli_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	129));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usli_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	130));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssri_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	131));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usri_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	132));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssli_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	129));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usli_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	130));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssri_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	131));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usri_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	132));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssli_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	129));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usli_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	130));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssri_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	131));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usri_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	132));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssli_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	129));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usli_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	130));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssri_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	131));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usri_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	132));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssli_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	129));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usli_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	130));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_ssri_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	131));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4070 */
rtx
gen_aarch64_usri_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	132));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshlu_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	114));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_sqshl_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	115));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4084 */
rtx
gen_aarch64_uqshl_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	116));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrun_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrun_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrn_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqshrn_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrn_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqrshrn_nv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrun_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrun_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrn_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqshrn_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrn_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqrshrn_nv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrun_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrun_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrn_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqshrn_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrn_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqrshrn_nv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrun_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrun_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrn_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqshrn_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrn_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqrshrn_nhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrun_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrun_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrn_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqshrn_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrn_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqrshrn_nsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrun_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	117));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrun_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	118));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqshrn_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	119));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqshrn_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	120));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_sqrshrn_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	121));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4098 */
rtx
gen_aarch64_uqrshrn_ndi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	122));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmltv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_LT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmlev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_LE (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmeqv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_EQ (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_GE (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgtv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_GT (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmltv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_LT (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmlev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_LE (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmeqv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_EQ (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_GE (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgtv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_GT (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmltv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmlev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LE (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmeqv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_EQ (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GE (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgtv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmltv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LT (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmlev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LE (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmeqv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_EQ (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GE (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgtv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GT (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmltv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmlev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LE (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmeqv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_EQ (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GE (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgtv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmltv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LT (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmlev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LE (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmeqv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_EQ (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GE (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgtv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GT (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmltv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LT (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmlev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LE (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmeqv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_EQ (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GE (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4114 */
rtx
gen_aarch64_cmgtv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GT (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
rtx
gen_aarch64_cmltdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LT (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
rtx
gen_aarch64_cmledi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LE (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
rtx
gen_aarch64_cmeqdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_EQ (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
rtx
gen_aarch64_cmgedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GE (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
rtx
gen_aarch64_cmgtdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GT (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmltuv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_LTU (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmleuv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_LEU (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgeuv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_GEU (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgtuv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8QImode,
	gen_rtx_GTU (V8QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmltuv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_LTU (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmleuv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_LEU (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgeuv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_GEU (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgtuv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V16QImode,
	gen_rtx_GTU (V16QImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmltuv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LTU (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmleuv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LEU (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgeuv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GEU (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgtuv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GTU (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmltuv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LTU (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmleuv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LEU (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgeuv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GEU (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgtuv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GTU (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmltuv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LTU (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmleuv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LEU (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgeuv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GEU (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgtuv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GTU (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmltuv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LTU (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmleuv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LEU (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgeuv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GEU (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgtuv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GTU (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmltuv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LTU (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmleuv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LEU (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgeuv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GEU (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4179 */
rtx
gen_aarch64_cmgtuv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GTU (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4191 */
rtx
gen_aarch64_cmltudi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LTU (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4191 */
rtx
gen_aarch64_cmleudi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LEU (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4191 */
rtx
gen_aarch64_cmgeudi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GEU (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4191 */
rtx
gen_aarch64_cmgtudi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GTU (DImode,
	operand1,
	operand2))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4246 */
rtx
gen_aarch64_cmtstv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8QImode,
	gen_rtx_EQ (V8QImode,
	gen_rtx_AND (V8QImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4246 */
rtx
gen_aarch64_cmtstv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V16QImode,
	gen_rtx_EQ (V16QImode,
	gen_rtx_AND (V16QImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4246 */
rtx
gen_aarch64_cmtstv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4HImode,
	gen_rtx_EQ (V4HImode,
	gen_rtx_AND (V4HImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4246 */
rtx
gen_aarch64_cmtstv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_EQ (V8HImode,
	gen_rtx_AND (V8HImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4246 */
rtx
gen_aarch64_cmtstv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2SImode,
	gen_rtx_EQ (V2SImode,
	gen_rtx_AND (V2SImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4246 */
rtx
gen_aarch64_cmtstv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_EQ (V4SImode,
	gen_rtx_AND (V4SImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4246 */
rtx
gen_aarch64_cmtstv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_EQ (V2DImode,
	gen_rtx_AND (V2DImode,
	operand1,
	operand2),
	operand3),
	operand4));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4261 */
rtx
gen_aarch64_cmtstdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_NE (DImode,
	gen_rtx_AND (DImode,
	operand1,
	operand2),
	const0_rtx))),
		gen_hard_reg_clobber (CCmode, 66)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmltv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmlev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LE (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmeqv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_EQ (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GE (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgtv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GT (V4HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmltv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LT (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmlev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LE (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmeqv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_EQ (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GE (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgtv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GT (V8HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmltv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmlev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LE (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmeqv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_EQ (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GE (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgtv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GT (V2SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmltv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LT (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmlev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LE (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmeqv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_EQ (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GE (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgtv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GT (V4SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmltv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LT (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmlev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LE (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmeqv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_EQ (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GE (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgtv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GT (V2DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmlthf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_LT (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmlehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_LE (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmeqhf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_EQ (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_GE (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgthf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_GT (HImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmltsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_LT (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmlesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_LE (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmeqsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_EQ (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_GE (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgtsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_GT (SImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmltdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LT (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmledf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LE (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmeqdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_EQ (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GE (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4314 */
rtx
gen_aarch64_cmgtdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GT (DImode,
	operand1,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facltv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LT (V4HImode,
	gen_rtx_ABS (V4HFmode,
	operand1),
	gen_rtx_ABS (V4HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_faclev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_LE (V4HImode,
	gen_rtx_ABS (V4HFmode,
	operand1),
	gen_rtx_ABS (V4HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GE (V4HImode,
	gen_rtx_ABS (V4HFmode,
	operand1),
	gen_rtx_ABS (V4HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgtv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4HImode,
	gen_rtx_GT (V4HImode,
	gen_rtx_ABS (V4HFmode,
	operand1),
	gen_rtx_ABS (V4HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facltv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LT (V8HImode,
	gen_rtx_ABS (V8HFmode,
	operand1),
	gen_rtx_ABS (V8HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_faclev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_LE (V8HImode,
	gen_rtx_ABS (V8HFmode,
	operand1),
	gen_rtx_ABS (V8HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GE (V8HImode,
	gen_rtx_ABS (V8HFmode,
	operand1),
	gen_rtx_ABS (V8HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgtv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V8HImode,
	gen_rtx_GT (V8HImode,
	gen_rtx_ABS (V8HFmode,
	operand1),
	gen_rtx_ABS (V8HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facltv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LT (V2SImode,
	gen_rtx_ABS (V2SFmode,
	operand1),
	gen_rtx_ABS (V2SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_faclev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_LE (V2SImode,
	gen_rtx_ABS (V2SFmode,
	operand1),
	gen_rtx_ABS (V2SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GE (V2SImode,
	gen_rtx_ABS (V2SFmode,
	operand1),
	gen_rtx_ABS (V2SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgtv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2SImode,
	gen_rtx_GT (V2SImode,
	gen_rtx_ABS (V2SFmode,
	operand1),
	gen_rtx_ABS (V2SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facltv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LT (V4SImode,
	gen_rtx_ABS (V4SFmode,
	operand1),
	gen_rtx_ABS (V4SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_faclev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_LE (V4SImode,
	gen_rtx_ABS (V4SFmode,
	operand1),
	gen_rtx_ABS (V4SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GE (V4SImode,
	gen_rtx_ABS (V4SFmode,
	operand1),
	gen_rtx_ABS (V4SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgtv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V4SImode,
	gen_rtx_GT (V4SImode,
	gen_rtx_ABS (V4SFmode,
	operand1),
	gen_rtx_ABS (V4SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facltv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LT (V2DImode,
	gen_rtx_ABS (V2DFmode,
	operand1),
	gen_rtx_ABS (V2DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_faclev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_LE (V2DImode,
	gen_rtx_ABS (V2DFmode,
	operand1),
	gen_rtx_ABS (V2DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GE (V2DImode,
	gen_rtx_ABS (V2DFmode,
	operand1),
	gen_rtx_ABS (V2DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgtv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (V2DImode,
	gen_rtx_GT (V2DImode,
	gen_rtx_ABS (V2DFmode,
	operand1),
	gen_rtx_ABS (V2DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_faclthf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_LT (HImode,
	gen_rtx_ABS (HFmode,
	operand1),
	gen_rtx_ABS (HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_faclehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_LE (HImode,
	gen_rtx_ABS (HFmode,
	operand1),
	gen_rtx_ABS (HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_GE (HImode,
	gen_rtx_ABS (HFmode,
	operand1),
	gen_rtx_ABS (HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgthf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (HImode,
	gen_rtx_GT (HImode,
	gen_rtx_ABS (HFmode,
	operand1),
	gen_rtx_ABS (HFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facltsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_LT (SImode,
	gen_rtx_ABS (SFmode,
	operand1),
	gen_rtx_ABS (SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_faclesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_LE (SImode,
	gen_rtx_ABS (SFmode,
	operand1),
	gen_rtx_ABS (SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_GE (SImode,
	gen_rtx_ABS (SFmode,
	operand1),
	gen_rtx_ABS (SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgtsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (SImode,
	gen_rtx_GT (SImode,
	gen_rtx_ABS (SFmode,
	operand1),
	gen_rtx_ABS (SFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facltdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LT (DImode,
	gen_rtx_ABS (DFmode,
	operand1),
	gen_rtx_ABS (DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facledf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LE (DImode,
	gen_rtx_ABS (DFmode,
	operand1),
	gen_rtx_ABS (DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GE (DImode,
	gen_rtx_ABS (DFmode,
	operand1),
	gen_rtx_ABS (DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4332 */
rtx
gen_aarch64_facgtdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GT (DImode,
	gen_rtx_ABS (DFmode,
	operand1),
	gen_rtx_ABS (DFmode,
	operand2))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4348 */
rtx
gen_aarch64_addpv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	135));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4348 */
rtx
gen_aarch64_addpv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	135));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4348 */
rtx
gen_aarch64_addpv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	135));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4359 */
rtx
gen_aarch64_addpdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	135));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4390 */
rtx
gen_aarch64_simd_ld2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4390 */
rtx
gen_aarch64_simd_ld2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4390 */
rtx
gen_aarch64_simd_ld2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4390 */
rtx
gen_aarch64_simd_ld2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4390 */
rtx
gen_aarch64_simd_ld2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4390 */
rtx
gen_aarch64_simd_ld2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4390 */
rtx
gen_aarch64_simd_ld2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4400 */
rtx
gen_aarch64_simd_ld2rdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	29));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4410 */
rtx
gen_aarch64_vec_load_lanesoi_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	34));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4444 */
rtx
gen_aarch64_simd_st2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4444 */
rtx
gen_aarch64_simd_st2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4444 */
rtx
gen_aarch64_simd_st2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4444 */
rtx
gen_aarch64_simd_st2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4444 */
rtx
gen_aarch64_simd_st2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4444 */
rtx
gen_aarch64_simd_st2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4444 */
rtx
gen_aarch64_simd_st2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4455 */
rtx
gen_aarch64_vec_store_lanesoi_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	50));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4488 */
rtx
gen_aarch64_simd_ld3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4488 */
rtx
gen_aarch64_simd_ld3v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4488 */
rtx
gen_aarch64_simd_ld3v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4488 */
rtx
gen_aarch64_simd_ld3v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4488 */
rtx
gen_aarch64_simd_ld3v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4488 */
rtx
gen_aarch64_simd_ld3v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4488 */
rtx
gen_aarch64_simd_ld3v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4498 */
rtx
gen_aarch64_simd_ld3rdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	31));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4508 */
rtx
gen_aarch64_vec_load_lanesci_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	35));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4542 */
rtx
gen_aarch64_simd_st3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4542 */
rtx
gen_aarch64_simd_st3v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4542 */
rtx
gen_aarch64_simd_st3v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4542 */
rtx
gen_aarch64_simd_st3v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4542 */
rtx
gen_aarch64_simd_st3v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4542 */
rtx
gen_aarch64_simd_st3v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4542 */
rtx
gen_aarch64_simd_st3v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4553 */
rtx
gen_aarch64_vec_store_lanesci_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	51));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4586 */
rtx
gen_aarch64_simd_ld4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4586 */
rtx
gen_aarch64_simd_ld4v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4586 */
rtx
gen_aarch64_simd_ld4v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4586 */
rtx
gen_aarch64_simd_ld4v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4586 */
rtx
gen_aarch64_simd_ld4v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4586 */
rtx
gen_aarch64_simd_ld4v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4586 */
rtx
gen_aarch64_simd_ld4v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4596 */
rtx
gen_aarch64_simd_ld4rdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	33));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4606 */
rtx
gen_aarch64_vec_load_lanesxi_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (4,
		operand1,
		operand2,
		operand3,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	36));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4640 */
rtx
gen_aarch64_simd_st4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4640 */
rtx
gen_aarch64_simd_st4v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4640 */
rtx
gen_aarch64_simd_st4v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4640 */
rtx
gen_aarch64_simd_st4v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4640 */
rtx
gen_aarch64_simd_st4v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4640 */
rtx
gen_aarch64_simd_st4v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4640 */
rtx
gen_aarch64_simd_st4v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4651 */
rtx
gen_aarch64_vec_store_lanesxi_lanedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (3,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61),
		operand2),
	52));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4684 */
rtx
gen_aarch64_rev_reglistoi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4684 */
rtx
gen_aarch64_rev_reglistci (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4684 */
rtx
gen_aarch64_rev_reglistxi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		operand2),
	165));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4738 */
rtx
gen_aarch64_be_ld1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	27));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4748 */
rtx
gen_aarch64_be_st1di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	46));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4870 */
rtx
gen_aarch64_ld2v8qi_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V32QImode,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4870 */
rtx
gen_aarch64_ld2v4hi_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V16HImode,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4870 */
rtx
gen_aarch64_ld2v4hf_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V16HFmode,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4870 */
rtx
gen_aarch64_ld2v2si_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V8SImode,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4870 */
rtx
gen_aarch64_ld2v2sf_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V8SFmode,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	28),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4888 */
rtx
gen_aarch64_ld2v8qi_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V32QImode,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	28)),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	28))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4888 */
rtx
gen_aarch64_ld2v4hi_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V16HImode,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	28)),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	28))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4888 */
rtx
gen_aarch64_ld2v4hf_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V16HFmode,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	28)),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	28))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4888 */
rtx
gen_aarch64_ld2v2si_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V8SImode,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	28)),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	28))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4888 */
rtx
gen_aarch64_ld2v2sf_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V8SFmode,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	28)),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	28))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_ld2di_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V4DImode,
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	28),
	const0_rtx),
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	28),
	const0_rtx)),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4906 */
rtx
gen_aarch64_ld2df_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V4DFmode,
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	28),
	const0_rtx),
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	28),
	const0_rtx)),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4924 */
rtx
gen_aarch64_ld2di_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V4DImode,
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	28)),
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	28))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4924 */
rtx
gen_aarch64_ld2df_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (OImode,
	gen_rtx_VEC_CONCAT (V4DFmode,
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	28)),
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	28))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4942 */
rtx
gen_aarch64_ld3v8qi_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V48QImode,
	gen_rtx_VEC_CONCAT (V32QImode,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4942 */
rtx
gen_aarch64_ld3v4hi_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V24HImode,
	gen_rtx_VEC_CONCAT (V16HImode,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4942 */
rtx
gen_aarch64_ld3v4hf_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V24HFmode,
	gen_rtx_VEC_CONCAT (V16HFmode,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4942 */
rtx
gen_aarch64_ld3v2si_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V12SImode,
	gen_rtx_VEC_CONCAT (V8SImode,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4942 */
rtx
gen_aarch64_ld3v2sf_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V12SFmode,
	gen_rtx_VEC_CONCAT (V8SFmode,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	30),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_aarch64_ld3v8qi_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V48QImode,
	gen_rtx_VEC_CONCAT (V32QImode,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	30)),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	30))),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	30))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_aarch64_ld3v4hi_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V24HImode,
	gen_rtx_VEC_CONCAT (V16HImode,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	30)),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	30))),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	30))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_aarch64_ld3v4hf_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V24HFmode,
	gen_rtx_VEC_CONCAT (V16HFmode,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	30)),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	30))),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	30))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_aarch64_ld3v2si_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V12SImode,
	gen_rtx_VEC_CONCAT (V8SImode,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	30)),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	30))),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	30))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4965 */
rtx
gen_aarch64_ld3v2sf_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V12SFmode,
	gen_rtx_VEC_CONCAT (V8SFmode,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	30)),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	30))),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	30))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4988 */
rtx
gen_aarch64_ld3di_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V6DImode,
	gen_rtx_VEC_CONCAT (V4DImode,
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	30),
	const0_rtx),
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	30),
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	30),
	const0_rtx)),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4988 */
rtx
gen_aarch64_ld3df_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V6DFmode,
	gen_rtx_VEC_CONCAT (V4DFmode,
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	30),
	const0_rtx),
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	30),
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	30),
	const0_rtx)),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5011 */
rtx
gen_aarch64_ld3di_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V6DImode,
	gen_rtx_VEC_CONCAT (V4DImode,
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	30)),
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	30))),
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	30))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5011 */
rtx
gen_aarch64_ld3df_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (CImode,
	gen_rtx_VEC_CONCAT (V6DFmode,
	gen_rtx_VEC_CONCAT (V4DFmode,
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	30)),
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	30))),
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	30))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5034 */
rtx
gen_aarch64_ld4v8qi_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V64QImode,
	gen_rtx_VEC_CONCAT (V32QImode,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V32QImode,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5034 */
rtx
gen_aarch64_ld4v4hi_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V32HImode,
	gen_rtx_VEC_CONCAT (V16HImode,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V16HImode,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5034 */
rtx
gen_aarch64_ld4v4hf_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V32HFmode,
	gen_rtx_VEC_CONCAT (V16HFmode,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V16HFmode,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5034 */
rtx
gen_aarch64_ld4v2si_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V16SImode,
	gen_rtx_VEC_CONCAT (V8SImode,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V8SImode,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5034 */
rtx
gen_aarch64_ld4v2sf_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V16SFmode,
	gen_rtx_VEC_CONCAT (V8SFmode,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx))),
	gen_rtx_VEC_CONCAT (V8SFmode,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	32),
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5062 */
rtx
gen_aarch64_ld4v8qi_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V64QImode,
	gen_rtx_VEC_CONCAT (V32QImode,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	32))),
	gen_rtx_VEC_CONCAT (V32QImode,
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V16QImode,
	gen_rtx_VEC_DUPLICATE (V8QImode,
	const0_rtx),
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	32)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5062 */
rtx
gen_aarch64_ld4v4hi_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V32HImode,
	gen_rtx_VEC_CONCAT (V16HImode,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	32))),
	gen_rtx_VEC_CONCAT (V16HImode,
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V8HImode,
	gen_rtx_VEC_DUPLICATE (V4HImode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	32)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5062 */
rtx
gen_aarch64_ld4v4hf_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V32HFmode,
	gen_rtx_VEC_CONCAT (V16HFmode,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	32))),
	gen_rtx_VEC_CONCAT (V16HFmode,
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V8HFmode,
	gen_rtx_VEC_DUPLICATE (V4HFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	32)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5062 */
rtx
gen_aarch64_ld4v2si_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V16SImode,
	gen_rtx_VEC_CONCAT (V8SImode,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	32))),
	gen_rtx_VEC_CONCAT (V8SImode,
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V4SImode,
	gen_rtx_VEC_DUPLICATE (V2SImode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	32)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5062 */
rtx
gen_aarch64_ld4v2sf_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V16SFmode,
	gen_rtx_VEC_CONCAT (V8SFmode,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	32))),
	gen_rtx_VEC_CONCAT (V8SFmode,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_VEC_DUPLICATE (V2SFmode,
	const0_rtx),
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	32)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5090 */
rtx
gen_aarch64_ld4di_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V8DImode,
	gen_rtx_VEC_CONCAT (V4DImode,
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32),
	const0_rtx),
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32),
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4DImode,
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32),
	const0_rtx),
	gen_rtx_VEC_CONCAT (V2DImode,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32),
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5090 */
rtx
gen_aarch64_ld4df_dreg_le (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V8DFmode,
	gen_rtx_VEC_CONCAT (V4DFmode,
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	32),
	const0_rtx),
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	32),
	const0_rtx)),
	gen_rtx_VEC_CONCAT (V4DFmode,
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	32),
	const0_rtx),
	gen_rtx_VEC_CONCAT (V2DFmode,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	32),
	const0_rtx))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5118 */
rtx
gen_aarch64_ld4di_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V8DImode,
	gen_rtx_VEC_CONCAT (V4DImode,
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32))),
	gen_rtx_VEC_CONCAT (V4DImode,
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V2DImode,
	const0_rtx,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	32)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5118 */
rtx
gen_aarch64_ld4df_dreg_be (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SUBREG (XImode,
	gen_rtx_VEC_CONCAT (V8DFmode,
	gen_rtx_VEC_CONCAT (V4DFmode,
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	32))),
	gen_rtx_VEC_CONCAT (V4DFmode,
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	32)),
	gen_rtx_VEC_CONCAT (V2DFmode,
	const0_rtx,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	32)))),
	0));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5280 */
rtx
gen_aarch64_tbl1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5280 */
rtx
gen_aarch64_tbl1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5292 */
rtx
gen_aarch64_tbl2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5302 */
rtx
gen_aarch64_tbl3v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5302 */
rtx
gen_aarch64_tbl3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5312 */
rtx
gen_aarch64_tbx4v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	137));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5312 */
rtx
gen_aarch64_tbx4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	137));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5325 */
rtx
gen_aarch64_qtbl3v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5325 */
rtx
gen_aarch64_qtbl3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5335 */
rtx
gen_aarch64_qtbx3v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	137));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5335 */
rtx
gen_aarch64_qtbx3v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	137));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5348 */
rtx
gen_aarch64_qtbl4v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5348 */
rtx
gen_aarch64_qtbl4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	136));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5358 */
rtx
gen_aarch64_qtbx4v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	137));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5358 */
rtx
gen_aarch64_qtbx4v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	137));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5369 */
rtx
gen_aarch64_combinev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		operand2),
	138));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	139));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_zip2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	140));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	143));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_trn2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	144));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp1v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	141));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5385 */
rtx
gen_aarch64_uzp2v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	142));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5396 */
rtx
gen_aarch64_extv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	145));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v8qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v4hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v8hi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev64v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	146));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev32v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	147));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5411 */
rtx
gen_aarch64_rev16v2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	148));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5420 */
rtx
gen_aarch64_st2v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5420 */
rtx
gen_aarch64_st2v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5420 */
rtx
gen_aarch64_st2v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5420 */
rtx
gen_aarch64_st2v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5420 */
rtx
gen_aarch64_st2v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5430 */
rtx
gen_aarch64_st2di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5430 */
rtx
gen_aarch64_st2df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5440 */
rtx
gen_aarch64_st3v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5440 */
rtx
gen_aarch64_st3v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5440 */
rtx
gen_aarch64_st3v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5440 */
rtx
gen_aarch64_st3v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5440 */
rtx
gen_aarch64_st3v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5450 */
rtx
gen_aarch64_st3di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5450 */
rtx
gen_aarch64_st3df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5460 */
rtx
gen_aarch64_st4v8qi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5460 */
rtx
gen_aarch64_st4v4hi_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5460 */
rtx
gen_aarch64_st4v4hf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5460 */
rtx
gen_aarch64_st4v2si_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5460 */
rtx
gen_aarch64_st4v2sf_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5470 */
rtx
gen_aarch64_st4di_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5470 */
rtx
gen_aarch64_st4df_dreg (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5579 */
rtx
gen_aarch64_frecpev4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5579 */
rtx
gen_aarch64_frecpev8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5579 */
rtx
gen_aarch64_frecpev2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5579 */
rtx
gen_aarch64_frecpev4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5579 */
rtx
gen_aarch64_frecpev2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5588 */
rtx
gen_aarch64_frecpehf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5588 */
rtx
gen_aarch64_frecpxhf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5588 */
rtx
gen_aarch64_frecpesf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5588 */
rtx
gen_aarch64_frecpxsf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5588 */
rtx
gen_aarch64_frecpedf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	12));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5588 */
rtx
gen_aarch64_frecpxdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	14));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5597 */
rtx
gen_aarch64_frecpsv4hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	13));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5597 */
rtx
gen_aarch64_frecpsv8hf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	13));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5597 */
rtx
gen_aarch64_frecpsv2sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	13));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5597 */
rtx
gen_aarch64_frecpsv4sf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	13));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5597 */
rtx
gen_aarch64_frecpsv2df (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	13));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5597 */
rtx
gen_aarch64_frecpshf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (HFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	13));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5597 */
rtx
gen_aarch64_frecpssf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	13));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5597 */
rtx
gen_aarch64_frecpsdf (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (2,
		operand1,
		operand2),
	13));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5608 */
rtx
gen_aarch64_urecpev2si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	11));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5608 */
rtx
gen_aarch64_urecpev4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	11));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5631 */
rtx
gen_aarch64_crypto_aesev16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	149));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5631 */
rtx
gen_aarch64_crypto_aesdv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	150));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5647 */
rtx
gen_aarch64_crypto_aesmcv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	151));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5647 */
rtx
gen_aarch64_crypto_aesimcv16qi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	152));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5664 */
rtx
gen_aarch64_crypto_sha1hsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (1,
		operand1),
	156));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5674 */
rtx
gen_aarch64_crypto_sha1su1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	158));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5684 */
rtx
gen_aarch64_crypto_sha1cv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	153));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5684 */
rtx
gen_aarch64_crypto_sha1mv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	154));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5684 */
rtx
gen_aarch64_crypto_sha1pv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	155));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5695 */
rtx
gen_aarch64_crypto_sha1su0v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	157));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5708 */
rtx
gen_aarch64_crypto_sha256hv4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	159));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5708 */
rtx
gen_aarch64_crypto_sha256h2v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	160));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5719 */
rtx
gen_aarch64_crypto_sha256su0v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	161));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5729 */
rtx
gen_aarch64_crypto_sha256su1v4si (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (3,
		operand1,
		operand2,
		operand3),
	162));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5742 */
rtx
gen_aarch64_crypto_pmulldi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (TImode,
	gen_rtvec (2,
		operand1,
		operand2),
	163));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5752 */
rtx
gen_aarch64_crypto_pmullv2di (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (TImode,
	gen_rtvec (2,
		operand1,
		operand2),
	164));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:39 */
rtx
gen_aarch64_compare_and_swapqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	11)),
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	11)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:39 */
rtx
gen_aarch64_compare_and_swaphi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	11)),
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	11)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:64 */
rtx
gen_aarch64_compare_and_swapsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	11)),
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	11)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:64 */
rtx
gen_aarch64_compare_and_swapdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	11)),
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	11)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:88 */
rtx
gen_aarch64_compare_and_swapqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	11)),
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	11))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:88 */
rtx
gen_aarch64_compare_and_swaphi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	11)),
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	11))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:114 */
rtx
gen_aarch64_compare_and_swapsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	11)),
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	11))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:114 */
rtx
gen_aarch64_compare_and_swapdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED,
	rtx operand4 ATTRIBUTE_UNUSED,
	rtx operand5 ATTRIBUTE_UNUSED,
	rtx operand6 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (gen_rtx_REG (CCmode,
	66),
	gen_rtx_UNSPEC_VOLATILE (CCmode,
	gen_rtvec (1,
		const0_rtx),
	11)),
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (5,
		operand2,
		operand3,
		operand4,
		operand5,
		operand6),
	11))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:160 */
rtx
gen_aarch64_atomic_exchangeqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	12)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:160 */
rtx
gen_aarch64_atomic_exchangehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	12)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:160 */
rtx
gen_aarch64_atomic_exchangesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	12)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:160 */
rtx
gen_aarch64_atomic_exchangedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	12)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:181 */
rtx
gen_aarch64_atomic_exchangeqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	12))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:181 */
rtx
gen_aarch64_atomic_exchangehi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	12))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:181 */
rtx
gen_aarch64_atomic_exchangesi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	12))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:181 */
rtx
gen_aarch64_atomic_exchangedi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	12))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_addqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_subqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_orqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_IOR (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_xorqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_XOR (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_andqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_AND (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_addhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_subhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_orhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_IOR (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_xorhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_XOR (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_andhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_AND (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_addsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_subsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_orsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_xorsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_andsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_adddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_subdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_ordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_IOR (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_xordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_XOR (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
rtx
gen_aarch64_atomic_anddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_AND (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_addqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_subqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_orqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_IOR (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_xorqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_XOR (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_andqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_AND (QImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_addhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_subhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_orhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_IOR (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_xorhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_XOR (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_andhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_AND (HImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_addsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_subsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_orsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_xorsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_andsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_adddi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_subdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_ordi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_IOR (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_xordi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_XOR (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
rtx
gen_aarch64_atomic_anddi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_AND (DImode,
	copy_rtx (operand0),
	operand1),
		operand2),
	15)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:261 */
rtx
gen_atomic_nandqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_NOT (QImode,
	gen_rtx_AND (QImode,
	copy_rtx (operand0),
	operand1)),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:261 */
rtx
gen_atomic_nandhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_NOT (HImode,
	gen_rtx_AND (HImode,
	copy_rtx (operand0),
	operand1)),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:261 */
rtx
gen_atomic_nandsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_NOT (SImode,
	gen_rtx_AND (SImode,
	copy_rtx (operand0),
	operand1)),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:261 */
rtx
gen_atomic_nanddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_NOT (DImode,
	gen_rtx_AND (DImode,
	copy_rtx (operand0),
	operand1)),
		operand2),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_addqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_subqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_orqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_IOR (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_xorqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_XOR (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_andqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_AND (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_addhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_subhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_orhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_IOR (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_xorhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_XOR (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_andhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_AND (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_addsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_subsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_orsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_xorsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_andsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_adddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_subdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_ordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_IOR (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_xordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_XOR (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
rtx
gen_aarch64_atomic_fetch_anddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_AND (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_addqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_PLUS (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_subqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_MINUS (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_orqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_IOR (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_xorqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_XOR (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_andqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_AND (QImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_addhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_PLUS (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_subhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_MINUS (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_orhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_IOR (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_xorhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_XOR (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_andhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_AND (HImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_addsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_PLUS (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_subsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_MINUS (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_orsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_IOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_xorsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_XOR (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_andsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_AND (SImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_adddi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_PLUS (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_subdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_MINUS (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_ordi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_IOR (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_xordi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_XOR (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
rtx
gen_aarch64_atomic_fetch_anddi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_AND (DImode,
	copy_rtx (operand1),
	operand2),
		operand3),
	16))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:349 */
rtx
gen_atomic_fetch_nandqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		gen_rtx_NOT (QImode,
	gen_rtx_AND (QImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:349 */
rtx
gen_atomic_fetch_nandhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		gen_rtx_NOT (HImode,
	gen_rtx_AND (HImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:349 */
rtx
gen_atomic_fetch_nandsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		gen_rtx_NOT (SImode,
	gen_rtx_AND (SImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:349 */
rtx
gen_atomic_fetch_nanddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (5,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		gen_rtx_NOT (DImode,
	gen_rtx_AND (DImode,
	copy_rtx (operand1),
	operand2)),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_add_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_sub_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_or_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_xor_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_and_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_AND (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_add_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_sub_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_or_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_xor_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_and_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_AND (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_add_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_sub_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_or_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_xor_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_and_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_add_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_sub_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_or_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_xor_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
rtx
gen_aarch64_atomic_and_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_add_fetchqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_sub_fetchqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_or_fetchqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_xor_fetchqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_and_fetchqi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_AND (QImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_add_fetchhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_sub_fetchhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_or_fetchhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_xor_fetchhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_and_fetchhi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_AND (HImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_add_fetchsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_sub_fetchsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_or_fetchsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_xor_fetchsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_and_fetchsi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_AND (SImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_add_fetchdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_sub_fetchdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_or_fetchdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_IOR (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_xor_fetchdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
rtx
gen_aarch64_atomic_and_fetchdi_lse (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_AND (DImode,
	operand1,
	operand2)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	16)),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:443 */
rtx
gen_atomic_nand_fetchqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_NOT (QImode,
	gen_rtx_AND (QImode,
	operand1,
	operand2))),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:443 */
rtx
gen_atomic_nand_fetchhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_NOT (HImode,
	gen_rtx_AND (HImode,
	operand1,
	operand2))),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:443 */
rtx
gen_atomic_nand_fetchsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_NOT (SImode,
	gen_rtx_AND (SImode,
	operand1,
	operand2))),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:443 */
rtx
gen_atomic_nand_fetchdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (4,
		gen_rtx_SET (operand0,
	gen_rtx_NOT (DImode,
	gen_rtx_AND (DImode,
	operand1,
	operand2))),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		copy_rtx (operand2),
		operand3),
	15)),
		gen_hard_reg_clobber (CCmode, 66),
		gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:467 */
rtx
gen_atomic_loadqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:467 */
rtx
gen_atomic_loadhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:467 */
rtx
gen_atomic_loadsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:467 */
rtx
gen_atomic_loaddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	9));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:483 */
rtx
gen_atomic_storeqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:483 */
rtx
gen_atomic_storehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:483 */
rtx
gen_atomic_storesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:483 */
rtx
gen_atomic_storedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	10));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:499 */
rtx
gen_aarch64_load_exclusiveqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand1,
		operand2),
	7)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:499 */
rtx
gen_aarch64_load_exclusivehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand1,
		operand2),
	7)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:516 */
rtx
gen_aarch64_load_exclusivesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand1,
		operand2),
	7));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:516 */
rtx
gen_aarch64_load_exclusivedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED)
{
  return gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand1,
		operand2),
	7));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:532 */
rtx
gen_aarch64_store_exclusiveqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	8)),
		gen_rtx_SET (operand1,
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	8))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:532 */
rtx
gen_aarch64_store_exclusivehi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	8)),
		gen_rtx_SET (operand1,
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	8))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:532 */
rtx
gen_aarch64_store_exclusivesi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	8)),
		gen_rtx_SET (operand1,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	8))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:532 */
rtx
gen_aarch64_store_exclusivedi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (1,
		const0_rtx),
	8)),
		gen_rtx_SET (operand1,
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	8))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:589 */
rtx
gen_aarch64_atomic_swpqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (2,
		operand2,
		operand3),
	14))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:589 */
rtx
gen_aarch64_atomic_swphi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (2,
		operand2,
		operand3),
	14))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:589 */
rtx
gen_aarch64_atomic_swpsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (2,
		operand2,
		operand3),
	14))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:589 */
rtx
gen_aarch64_atomic_swpdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (2,
		operand2,
		operand3),
	14))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:612 */
rtx
gen_aarch64_atomic_casqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand2,
		operand3),
	13))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:612 */
rtx
gen_aarch64_atomic_cashi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1)),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand2,
		operand3),
	13))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:637 */
rtx
gen_aarch64_atomic_cassi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand2,
		operand3),
	13))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:637 */
rtx
gen_aarch64_atomic_casdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand0),
		operand2,
		operand3),
	13))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadsetqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	17))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadclrqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	18))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadeorqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	19))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadaddqi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (QImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	20))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadsethi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	17))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadclrhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	18))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadeorhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	19))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadaddhi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (HImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	20))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadsetsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	17))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadclrsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	18))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadeorsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	19))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadaddsi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (SImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	20))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadsetdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	17))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadclrdi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	18))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadeordi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	19))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:661 */
rtx
gen_aarch64_atomic_loadadddi (rtx operand0 ATTRIBUTE_UNUSED,
	rtx operand1 ATTRIBUTE_UNUSED,
	rtx operand2 ATTRIBUTE_UNUSED,
	rtx operand3 ATTRIBUTE_UNUSED)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (copy_rtx (operand1),
	gen_rtx_UNSPEC_VOLATILE (DImode,
	gen_rtvec (3,
		copy_rtx (operand1),
		operand2,
		operand3),
	20))));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:241 */
rtx
gen_cbranchsi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 248 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
					 operands[2]);
  operands[2] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:241 */
rtx
gen_cbranchdi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 248 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
					 operands[2]);
  operands[2] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:255 */
rtx
gen_cbranchsf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 262 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
					 operands[2]);
  operands[2] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:255 */
rtx
gen_cbranchdf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 262 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
					 operands[2]);
  operands[2] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_jump_insn (gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:269 */
rtx
gen_cbranchcc4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (pc_rtx,
	gen_rtx_IF_THEN_ELSE (VOIDmode,
	gen_rtx_fmt_ee (GET_CODE (operand0), VOIDmode,
		operand1,
		operand2),
	gen_rtx_LABEL_REF (VOIDmode,
	operand3),
	pc_rtx));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:334 */
rtx
gen_modsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 339 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT val = INTVAL (operands[2]);

    if (val <= 0
       || exact_log2 (val) <= 0
       || !aarch64_bitmask_imm (val - 1, SImode))
      FAIL;

    rtx mask = GEN_INT (val - 1);

    /* In the special case of x0 % 2 we can do the even shorter:
	cmp    x0, xzr
	and    x0, x0, 1
	cneg   x0, x0, lt.  */
    if (val == 2)
      {
	rtx masked = gen_reg_rtx (SImode);
	rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
	emit_insn (gen_andsi3 (masked, operands[1], mask));
	rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
	emit_insn (gen_csneg3si_insn (operands[0], x, masked, masked));
	DONE;
      }

    rtx neg_op = gen_reg_rtx (SImode);
    rtx_insn *insn = emit_insn (gen_negsi2_compare0 (neg_op, operands[1]));

    /* Extract the condition register and mode.  */
    rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
    rtx cc_reg = SET_DEST (cmp);
    rtx cond = gen_rtx_GE (VOIDmode, cc_reg, const0_rtx);

    rtx masked_pos = gen_reg_rtx (SImode);
    emit_insn (gen_andsi3 (masked_pos, operands[1], mask));

    rtx masked_neg = gen_reg_rtx (SImode);
    emit_insn (gen_andsi3 (masked_neg, neg_op, mask));

    emit_insn (gen_csneg3si_insn (operands[0], cond,
				       masked_neg, masked_pos));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:334 */
rtx
gen_moddi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 339 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT val = INTVAL (operands[2]);

    if (val <= 0
       || exact_log2 (val) <= 0
       || !aarch64_bitmask_imm (val - 1, DImode))
      FAIL;

    rtx mask = GEN_INT (val - 1);

    /* In the special case of x0 % 2 we can do the even shorter:
	cmp    x0, xzr
	and    x0, x0, 1
	cneg   x0, x0, lt.  */
    if (val == 2)
      {
	rtx masked = gen_reg_rtx (DImode);
	rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
	emit_insn (gen_anddi3 (masked, operands[1], mask));
	rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
	emit_insn (gen_csneg3di_insn (operands[0], x, masked, masked));
	DONE;
      }

    rtx neg_op = gen_reg_rtx (DImode);
    rtx_insn *insn = emit_insn (gen_negdi2_compare0 (neg_op, operands[1]));

    /* Extract the condition register and mode.  */
    rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
    rtx cc_reg = SET_DEST (cmp);
    rtx cond = gen_rtx_GE (VOIDmode, cc_reg, const0_rtx);

    rtx masked_pos = gen_reg_rtx (DImode);
    emit_insn (gen_anddi3 (masked_pos, operands[1], mask));

    rtx masked_neg = gen_reg_rtx (DImode);
    emit_insn (gen_anddi3 (masked_neg, neg_op, mask));

    emit_insn (gen_csneg3di_insn (operands[0], cond,
				       masked_neg, masked_pos));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:418 */
extern rtx_insn *gen_split_1 (rtx_insn *, rtx *);
rtx_insn *
gen_split_1 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_1\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, SImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:418 */
extern rtx_insn *gen_split_2 (rtx_insn *, rtx *);
rtx_insn *
gen_split_2 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_2\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, SImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:418 */
extern rtx_insn *gen_split_3 (rtx_insn *, rtx *);
rtx_insn *
gen_split_3 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_3\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, SImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:418 */
extern rtx_insn *gen_split_4 (rtx_insn *, rtx *);
rtx_insn *
gen_split_4 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_4\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, SImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:418 */
extern rtx_insn *gen_split_5 (rtx_insn *, rtx *);
rtx_insn *
gen_split_5 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_5\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, DImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:418 */
extern rtx_insn *gen_split_6 (rtx_insn *, rtx *);
rtx_insn *
gen_split_6 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_6\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, DImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:418 */
extern rtx_insn *gen_split_7 (rtx_insn *, rtx *);
rtx_insn *
gen_split_7 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_7\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, DImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:418 */
extern rtx_insn *gen_split_8 (rtx_insn *, rtx *);
rtx_insn *
gen_split_8 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_8\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 430 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[0], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, DImode, cc_reg, const0_rtx);
    emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:443 */
rtx
gen_casesi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 450 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (operands[1] != const0_rtx)
      {
	rtx reg = gen_reg_rtx (SImode);

	/* Canonical RTL says that if you have:

	   (minus (X) (CONST))

           then this should be emitted as:

           (plus (X) (-CONST))

	   The use of trunc_int_for_mode ensures that the resulting
	   constant can be represented in SImode, this is important
	   for the corner case where operand[1] is INT_MIN.  */

	operands[1] = GEN_INT (trunc_int_for_mode (-INTVAL (operands[1]), SImode));

	if (!(*insn_data[CODE_FOR_addsi3].operand[2].predicate)
	      (operands[1], SImode))
	  operands[1] = force_reg (SImode, operands[1]);
	emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
	operands[0] = reg;
      }

    if (!aarch64_plus_operand (operands[2], SImode))
      operands[2] = force_reg (SImode, operands[2]);
    emit_jump_insn (gen_cbranchsi4 (gen_rtx_GTU (SImode, const0_rtx,
						 const0_rtx),
				    operands[0], operands[2], operands[4]));

    operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
    emit_jump_insn (gen_casesi_dispatch (operands[2], operands[0],
					 operands[3]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:547 */
rtx
gen_prologue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 550 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  aarch64_expand_prologue ();
  DONE;
  
#undef DONE
#undef FAIL
  }
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	const0_rtx));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:556 */
rtx
gen_epilogue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 559 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  aarch64_expand_epilogue (false);
  DONE;
  
#undef DONE
#undef FAIL
  }
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	const0_rtx));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:565 */
rtx
gen_sibcall_epilogue (void)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 568 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  aarch64_expand_epilogue (true);
  DONE;
  
#undef DONE
#undef FAIL
  }
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	const0_rtx));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:581 */
rtx
gen_return (void)
{
  return simple_return_rtx;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:603 */
extern rtx_insn *gen_split_9 (rtx_insn *, rtx *);
rtx_insn *
gen_split_9 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_9\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 608 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    operands[1] = aarch64_final_eh_return_addr ();
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  emit_insn (gen_rtx_SET (operand1,
	operand0));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:720 */
rtx
gen_call_internal (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2),
		gen_hard_reg_clobber (DImode, 30)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:726 */
rtx
gen_call (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 732 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  {
    rtx callee, pat;

    /* In an untyped call, we can get NULL for operand 2.  */
    if (operands[2] == NULL)
      operands[2] = const0_rtx;

    /* Decide if we should generate indirect calls by loading the
       64-bit address of the callee into a register before performing
       the branch-and-link.  */
    callee = XEXP (operands[0], 0);
    if (GET_CODE (callee) == SYMBOL_REF
	? (aarch64_is_long_call_p (callee)
	   || aarch64_is_noplt_call_p (callee))
	: !REG_P (callee))
      XEXP (operands[0], 0) = force_reg (Pmode, callee);

    pat = gen_call_internal (operands[0], operands[1], operands[2]);
    aarch64_emit_call_insn (pat);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	operand1),
		gen_rtx_USE (VOIDmode,
	operand2),
		gen_hard_reg_clobber (DImode, 30))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:778 */
rtx
gen_call_value_internal (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	operand1,
	operand2)),
		gen_rtx_USE (VOIDmode,
	operand3),
		gen_hard_reg_clobber (DImode, 30)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:785 */
rtx
gen_call_value (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 792 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  {
    rtx callee, pat;

    /* In an untyped call, we can get NULL for operand 3.  */
    if (operands[3] == NULL)
      operands[3] = const0_rtx;

    /* Decide if we should generate indirect calls by loading the
       64-bit address of the callee into a register before performing
       the branch-and-link.  */
    callee = XEXP (operands[1], 0);
    if (GET_CODE (callee) == SYMBOL_REF
	? (aarch64_is_long_call_p (callee)
	   || aarch64_is_noplt_call_p (callee))
	: !REG_P (callee))
      XEXP (operands[1], 0) = force_reg (Pmode, callee);

    pat = gen_call_value_internal (operands[0], operands[1], operands[2],
                                   operands[3]);
    aarch64_emit_call_insn (pat);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	operand1,
	operand2)),
		gen_rtx_USE (VOIDmode,
	operand3),
		gen_hard_reg_clobber (DImode, 30))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:842 */
rtx
gen_sibcall_internal (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	operand1),
		ret_rtx,
		gen_rtx_USE (VOIDmode,
	operand2)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:848 */
rtx
gen_sibcall (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 854 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx pat;
    rtx callee = XEXP (operands[0], 0);
    if (!REG_P (callee)
       && ((GET_CODE (callee) != SYMBOL_REF)
	   || aarch64_is_noplt_call_p (callee)))
      XEXP (operands[0], 0) = force_reg (Pmode, callee);

    if (operands[2] == NULL_RTX)
      operands[2] = const0_rtx;

    pat = gen_sibcall_internal (operands[0], operands[1], operands[2]);
    aarch64_emit_call_insn (pat);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	operand1),
		ret_rtx,
		gen_rtx_USE (VOIDmode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:871 */
rtx
gen_sibcall_value_internal (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	operand1,
	operand2)),
		ret_rtx,
		gen_rtx_USE (VOIDmode,
	operand3)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:878 */
rtx
gen_sibcall_value (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 885 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx pat;
    rtx callee = XEXP (operands[1], 0);
    if (!REG_P (callee)
       && ((GET_CODE (callee) != SYMBOL_REF)
	   || aarch64_is_noplt_call_p (callee)))
      XEXP (operands[1], 0) = force_reg (Pmode, callee);

    if (operands[3] == NULL_RTX)
      operands[3] = const0_rtx;

    pat = gen_sibcall_value_internal (operands[0], operands[1], operands[2],
                                      operands[3]);
    aarch64_emit_call_insn (pat);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	operand1,
	operand2)),
		ret_rtx,
		gen_rtx_USE (VOIDmode,
	operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:931 */
rtx
gen_untyped_call (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 937 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  int i;

  emit_call_insn (gen_call (operands[0], const0_rtx, NULL));

  for (i = 0; i < XVECLEN (operands[2], 0); i++)
    {
      rtx set = XVECEXP (operands[2], 0, i);
      emit_move_insn (SET_DEST (set), SET_SRC (set));
    }

  /* The optimizer does not know that the call sets the function value
     registers we stored in the result block.  We avoid problems by
     claiming that all hard registers are used and clobbered at this
     point.  */
  emit_insn (gen_blockage ());
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_CALL (VOIDmode,
	operand0,
	const0_rtx),
		operand1,
		operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:960 */
rtx
gen_movqi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 964 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (QImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:960 */
rtx
gen_movhi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 964 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (HImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1008 */
rtx
gen_movsi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1012 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (SImode, operands[1]);

    /* FIXME: RR we still need to fix up what we are doing with
       symbol_refs and other types of constants.  */
    if (CONSTANT_P (operands[1])
        && !CONST_INT_P (operands[1]))
     {
       aarch64_expand_mov_immediate (operands[0], operands[1]);
       DONE;
     }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1008 */
rtx
gen_movdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1012 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (DImode, operands[1]);

    /* FIXME: RR we still need to fix up what we are doing with
       symbol_refs and other types of constants.  */
    if (CONSTANT_P (operands[1])
        && !CONST_INT_P (operands[1]))
     {
       aarch64_expand_mov_immediate (operands[0], operands[1]);
       DONE;
     }
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1027 */
extern rtx_insn *gen_split_10 (rtx_insn *, rtx *);
rtx_insn *
gen_split_10 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_10\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1050 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
       aarch64_expand_mov_immediate (operands[0], operands[1]);
       DONE;
    }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1059 */
extern rtx_insn *gen_split_11 (rtx_insn *, rtx *);
rtx_insn *
gen_split_11 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_11\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1083 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
       aarch64_expand_mov_immediate (operands[0], operands[1]);
       DONE;
    }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1104 */
rtx
gen_movti (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1108 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

    if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
      operands[1] = force_reg (TImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1141 */
extern rtx_insn *gen_split_12 (rtx_insn *, rtx *);
rtx_insn *
gen_split_12 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_12\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1146 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  aarch64_split_128bit_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1151 */
rtx
gen_movhf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1155 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (!TARGET_FLOAT)
      {
	aarch64_err_no_fpadvsimd (HFmode, "code");
	FAIL;
      }

    if (GET_CODE (operands[0]) == MEM
        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
	      && aarch64_float_const_zero_rtx_p (operands[1])))
      operands[1] = force_reg (HFmode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1151 */
rtx
gen_movsf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1155 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (!TARGET_FLOAT)
      {
	aarch64_err_no_fpadvsimd (SFmode, "code");
	FAIL;
      }

    if (GET_CODE (operands[0]) == MEM
        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
	      && aarch64_float_const_zero_rtx_p (operands[1])))
      operands[1] = force_reg (SFmode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1151 */
rtx
gen_movdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1155 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (!TARGET_FLOAT)
      {
	aarch64_err_no_fpadvsimd (DFmode, "code");
	FAIL;
      }

    if (GET_CODE (operands[0]) == MEM
        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
	      && aarch64_float_const_zero_rtx_p (operands[1])))
      operands[1] = force_reg (DFmode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1151 */
rtx
gen_movtf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1155 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (!TARGET_FLOAT)
      {
	aarch64_err_no_fpadvsimd (TFmode, "code");
	FAIL;
      }

    if (GET_CODE (operands[0]) == MEM
        && ! (GET_CODE (operands[1]) == CONST_DOUBLE
	      && aarch64_float_const_zero_rtx_p (operands[1])))
      operands[1] = force_reg (TFmode, operands[1]);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1256 */
extern rtx_insn *gen_split_13 (rtx_insn *, rtx *);
rtx_insn *
gen_split_13 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_13\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1261 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    aarch64_split_128bit_move (operands[0], operands[1]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1272 */
rtx
gen_movmemdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1278 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_expand_movmem (operands))
    DONE;
  FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1492 */
rtx
gen_extendsidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1492 */
rtx
gen_zero_extendsidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1544 */
rtx
gen_extendqisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1544 */
rtx
gen_zero_extendqisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1544 */
rtx
gen_extendqidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1544 */
rtx
gen_zero_extendqidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1544 */
rtx
gen_extendhisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1544 */
rtx
gen_zero_extendhisi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (SImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1544 */
rtx
gen_extendhidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1544 */
rtx
gen_zero_extendhidi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1571 */
rtx
gen_extendqihi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1571 */
rtx
gen_zero_extendqihi2 (rtx operand0,
	rtx operand1)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (HImode,
	operand1));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1601 */
rtx
gen_addsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1607 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_pluslong_strict_immedate (operands[2], SImode))
    {
      /* Give CSE the opportunity to share this constant across additions.  */
      if (!cse_not_expected && can_create_pseudo_p ())
        operands[2] = force_reg (SImode, operands[2]);

      /* Split will refuse to operate on a modification to the stack pointer.
	 Aid the prologue and epilogue expanders by splitting this now.  */
      else if (reload_completed && operands[0] == stack_pointer_rtx)
	{
	  HOST_WIDE_INT i = INTVAL (operands[2]);
	  HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
	  emit_insn (gen_rtx_SET (operands[0],
				  gen_rtx_PLUS (SImode, operands[1],
						GEN_INT (i - s))));
	  operands[1] = operands[0];
	  operands[2] = GEN_INT (s);
	}
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1601 */
rtx
gen_adddi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1607 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_pluslong_strict_immedate (operands[2], DImode))
    {
      /* Give CSE the opportunity to share this constant across additions.  */
      if (!cse_not_expected && can_create_pseudo_p ())
        operands[2] = force_reg (DImode, operands[2]);

      /* Split will refuse to operate on a modification to the stack pointer.
	 Aid the prologue and epilogue expanders by splitting this now.  */
      else if (reload_completed && operands[0] == stack_pointer_rtx)
	{
	  HOST_WIDE_INT i = INTVAL (operands[2]);
	  HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
	  emit_insn (gen_rtx_SET (operands[0],
				  gen_rtx_PLUS (DImode, operands[1],
						GEN_INT (i - s))));
	  operands[1] = operands[0];
	  operands[2] = GEN_INT (s);
	}
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1664 */
extern rtx_insn *gen_peephole2_1 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_1 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[3] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_1\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	copy_rtx (operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1664 */
extern rtx_insn *gen_peephole2_2 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_2 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[3] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_2\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	copy_rtx (operand3))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1675 */
extern rtx_insn *gen_peephole2_3 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_3 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[3] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_3\n");
  start_sequence ();
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	operand2));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_PLUS (SImode,
	operand1,
	copy_rtx (operand3)))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1689 */
extern rtx_insn *gen_split_14 (rtx_insn *, rtx *);
rtx_insn *
gen_split_14 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_14\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1697 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT i = INTVAL (operands[2]);
    HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
    operands[3] = GEN_INT (i - s);
    operands[4] = GEN_INT (s);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_PLUS (SImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1689 */
extern rtx_insn *gen_split_15 (rtx_insn *, rtx *);
rtx_insn *
gen_split_15 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_15\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1697 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT i = INTVAL (operands[2]);
    HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
    operands[3] = GEN_INT (i - s);
    operands[4] = GEN_INT (s);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_PLUS (DImode,
	copy_rtx (operand0),
	operand4)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1705 */
extern rtx_insn *gen_split_16 (rtx_insn *, rtx *);
rtx_insn *
gen_split_16 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx operand4;
  rtx operand5;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_16\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1714 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT i = INTVAL (operands[2]);
    HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
    operands[3] = GEN_INT (i - s);
    operands[4] = GEN_INT (s);
    operands[5] = gen_lowpart (SImode, operands[0]);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  operand4 = operands[4];
  (void) operand4;
  operand5 = operands[5];
  (void) operand5;
  emit_insn (gen_rtx_SET (operand5,
	gen_rtx_PLUS (SImode,
	operand1,
	operand3)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	gen_rtx_PLUS (SImode,
	copy_rtx (operand5),
	operand4))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:1723 */
rtx
gen_addti3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1728 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_adddi3_compareC (low, gen_lowpart (DImode, operands[1]),
				  gen_lowpart (DImode, operands[2])));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_adddi3_carryin (high, gen_highpart (DImode, operands[1]),
				 gen_highpart (DImode, operands[2])));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (TImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2159 */
rtx
gen_addsi3_carryin (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (SImode,
	gen_rtx_PLUS (SImode,
	gen_rtx_NE (SImode,
	gen_rtx_REG (CC_Cmode,
	66),
	const0_rtx),
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2159 */
rtx
gen_adddi3_carryin (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_PLUS (DImode,
	gen_rtx_PLUS (DImode,
	gen_rtx_NE (DImode,
	gen_rtx_REG (CC_Cmode,
	66),
	const0_rtx),
	operand1),
	operand2));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2295 */
rtx
gen_subti3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2300 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_subdi3_compare1 (low, gen_lowpart (DImode, operands[1]),
				  gen_lowpart (DImode, operands[2])));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_subdi3_carryin (high, gen_highpart (DImode, operands[1]),
				 gen_highpart (DImode, operands[2])));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MINUS (TImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2501 */
rtx
gen_subsi3_carryin (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (SImode,
	gen_rtx_MINUS (SImode,
	operand1,
	operand2),
	gen_rtx_LTU (SImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2501 */
rtx
gen_subdi3_carryin (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  return gen_rtx_SET (operand0,
	gen_rtx_MINUS (DImode,
	gen_rtx_MINUS (DImode,
	operand1,
	operand2),
	gen_rtx_LTU (DImode,
	gen_rtx_REG (CCmode,
	66),
	const0_rtx)));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2630 */
rtx
gen_abssi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2634 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
    rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
    emit_insn (gen_csneg3si_insn (operands[0], x, operands[1], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2630 */
rtx
gen_absdi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2634 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
    rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
    emit_insn (gen_csneg3di_insn (operands[0], x, operands[1], operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2894 */
rtx
gen_mulditi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2899 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_muldi3 (low, operands[1], operands[2]));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_smuldi3_highpart (high, operands[1], operands[2]));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	gen_rtx_SIGN_EXTEND (TImode,
	operand1),
	gen_rtx_SIGN_EXTEND (TImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2894 */
rtx
gen_umulditi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2899 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx low = gen_reg_rtx (DImode);
  emit_insn (gen_muldi3 (low, operands[1], operands[2]));

  rtx high = gen_reg_rtx (DImode);
  emit_insn (gen_umuldi3_highpart (high, operands[1], operands[2]));

  emit_move_insn (gen_lowpart (DImode, operands[0]), low);
  emit_move_insn (gen_highpart (DImode, operands[0]), high);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	gen_rtx_ZERO_EXTEND (TImode,
	operand1),
	gen_rtx_ZERO_EXTEND (TImode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:2913 */
rtx
gen_multi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2918 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx l0 = gen_reg_rtx (DImode);
  rtx l1 = gen_lowpart (DImode, operands[1]);
  rtx l2 = gen_lowpart (DImode, operands[2]);
  rtx h0 = gen_reg_rtx (DImode);
  rtx h1 = gen_highpart (DImode, operands[1]);
  rtx h2 = gen_highpart (DImode, operands[2]);

  emit_insn (gen_muldi3 (l0, l1, l2));
  emit_insn (gen_umuldi3_highpart (h0, l1, l2));
  emit_insn (gen_madddi (h0, h1, l2, h0));
  emit_insn (gen_madddi (h0, l1, h2, h0));

  emit_move_insn (gen_lowpart (DImode, operands[0]), l0);
  emit_move_insn (gen_highpart (DImode, operands[0]), h0);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MULT (TImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3044 */
rtx
gen_cstoresi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3050 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3044 */
rtx
gen_cstoredi4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3050 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3057 */
rtx
gen_cstorecc4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3063 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  emit_insn (gen_rtx_SET (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3069 */
rtx
gen_cstoresf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3075 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3069 */
rtx
gen_cstoredf4 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3075 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_fmt_ee (GET_CODE (operand1), SImode,
		operand2,
		operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3101 */
extern rtx_insn *gen_split_17 (rtx_insn *, rtx *);
rtx_insn *
gen_split_17 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_17\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3111 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[2]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[2]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, SImode, cc_reg, const0_rtx);
    emit_insn (gen_aarch64_cstoresi (operands[0], cmp_rtx, cc_reg));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3101 */
extern rtx_insn *gen_split_18 (rtx_insn *, rtx *);
rtx_insn *
gen_split_18 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_18\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3111 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[2]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[2]) & 0xfff000;
    rtx tmp = gen_reg_rtx (SImode);
    emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-hi_imm)));
    emit_insn (gen_addsi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, SImode, cc_reg, const0_rtx);
    emit_insn (gen_aarch64_cstoresi (operands[0], cmp_rtx, cc_reg));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3101 */
extern rtx_insn *gen_split_19 (rtx_insn *, rtx *);
rtx_insn *
gen_split_19 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_19\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3111 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[2]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[2]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (EQ, DImode, cc_reg, const0_rtx);
    emit_insn (gen_aarch64_cstoredi (operands[0], cmp_rtx, cc_reg));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3101 */
extern rtx_insn *gen_split_20 (rtx_insn *, rtx *);
rtx_insn *
gen_split_20 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_20\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3111 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    HOST_WIDE_INT lo_imm = UINTVAL (operands[2]) & 0xfff;
    HOST_WIDE_INT hi_imm = UINTVAL (operands[2]) & 0xfff000;
    rtx tmp = gen_reg_rtx (DImode);
    emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (-hi_imm)));
    emit_insn (gen_adddi3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
    rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
    rtx cmp_rtx = gen_rtx_fmt_ee (NE, DImode, cc_reg, const0_rtx);
    emit_insn (gen_aarch64_cstoredi (operands[0], cmp_rtx, cc_reg));
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3156 */
rtx
gen_cmovsi6 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3165 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3),
	operand4,
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3156 */
rtx
gen_cmovdi6 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3165 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3),
	operand4,
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3172 */
rtx
gen_cmovsf6 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3181 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3),
	operand4,
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3172 */
rtx
gen_cmovdf6 (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3181 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
				      operands[3]);
  operands[3] = const0_rtx;
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand1), VOIDmode,
		operand2,
		operand3),
	operand4,
	operand5)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3256 */
rtx
gen_movqicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3262 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				     XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (QImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3256 */
rtx
gen_movhicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3262 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				     XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (HImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3256 */
rtx
gen_movsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3262 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				     XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3256 */
rtx
gen_movdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3262 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				     XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3275 */
rtx
gen_movsfsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3281 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3275 */
rtx
gen_movsfdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3281 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3275 */
rtx
gen_movdfsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3281 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3275 */
rtx
gen_movdfdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3281 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3294 */
rtx
gen_movsfcc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3300 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SFmode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3294 */
rtx
gen_movdfcc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3300 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				  XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DFmode,
	operand1,
	operand2,
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3313 */
rtx
gen_negsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3319 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				      XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_NEG (SImode,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3313 */
rtx
gen_notsicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3319 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				      XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (SImode,
	operand1,
	gen_rtx_NOT (SImode,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3313 */
rtx
gen_negdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3319 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				      XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	gen_rtx_NEG (DImode,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3313 */
rtx
gen_notdicc (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3319 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg;
    enum rtx_code code = GET_CODE (operands[1]);

    if (code == UNEQ || code == LTGT)
      FAIL;

    ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0),
				      XEXP (operands[1], 1));
    operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	operand1,
	gen_rtx_NOT (DImode,
	operand2),
	operand3)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3599 */
extern rtx_insn *gen_split_21 (rtx_insn *, rtx *);
rtx_insn *
gen_split_21 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_21\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3612 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_XOR (SImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_NOT (SImode,
	copy_rtx (operand0))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3599 */
extern rtx_insn *gen_split_22 (rtx_insn *, rtx *);
rtx_insn *
gen_split_22 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_22\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3612 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_XOR (DImode,
	operand1,
	operand2)));
  emit_insn (gen_rtx_SET (copy_rtx (operand0),
	gen_rtx_NOT (DImode,
	copy_rtx (operand0))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3755 */
rtx
gen_ffssi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ffssi2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3759 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg = aarch64_gen_compare_reg (EQ, operands[1], const0_rtx);
    rtx x = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);

    emit_insn (gen_rbitsi2 (operands[0], operands[1]));
    emit_insn (gen_clzsi2 (operands[0], operands[0]));
    emit_insn (gen_csinc3si_insn (operands[0], x, operands[0], const0_rtx));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3755 */
rtx
gen_ffsdi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ffsdi2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3759 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx ccreg = aarch64_gen_compare_reg (EQ, operands[1], const0_rtx);
    rtx x = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);

    emit_insn (gen_rbitdi2 (operands[0], operands[1]));
    emit_insn (gen_clzdi2 (operands[0], operands[0]));
    emit_insn (gen_csinc3di_insn (operands[0], x, operands[0], const0_rtx));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3791 */
extern rtx_insn *gen_split_23 (rtx_insn *, rtx *);
rtx_insn *
gen_split_23 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_23\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3798 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  emit_insn (gen_rbitsi2 (operands[0], operands[1]));
  emit_insn (gen_clzsi2 (operands[0], operands[0]));
  DONE;

#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3791 */
extern rtx_insn *gen_split_24 (rtx_insn *, rtx *);
rtx_insn *
gen_split_24 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_24\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3798 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"

  emit_insn (gen_rbitdi2 (operands[0], operands[1]));
  emit_insn (gen_clzdi2 (operands[0], operands[0]));
  DONE;

#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3878 */
rtx
gen_ashlsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3883 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (SImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3878 */
rtx
gen_ashrsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3883 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (SImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3878 */
rtx
gen_lshrsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3883 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (SImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3878 */
rtx
gen_ashldi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3883 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (DImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3878 */
rtx
gen_ashrdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3883 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (DImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFTRT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3878 */
rtx
gen_lshrdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3883 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (DImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LSHIFTRT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3898 */
rtx
gen_ashlqi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3903 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    operands[2] = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (QImode));

    if (operands[2] == const0_rtx)
      {
	emit_insn (gen_movqi (operands[0], operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (QImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3898 */
rtx
gen_ashlhi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3903 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    operands[2] = GEN_INT (INTVAL (operands[2]) & GET_MODE_MASK (HImode));

    if (operands[2] == const0_rtx)
      {
	emit_insn (gen_movhi (operands[0], operands[1]));
	DONE;
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ASHIFT (HImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3914 */
rtx
gen_rotrsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3919 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (SImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3914 */
rtx
gen_rotrdi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3919 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT (INTVAL (operands[2])
                               & (GET_MODE_BITSIZE (DImode) - 1));

        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3934 */
rtx
gen_rotlsi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3939 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    /* (SZ - cnt) % SZ == -cnt % SZ */
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT ((-INTVAL (operands[2]))
			       & (GET_MODE_BITSIZE (SImode) - 1));
        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movsi (operands[0], operands[1]));
	    DONE;
          }
      }
    else
      operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					NULL_RTX, 1);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (SImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3934 */
rtx
gen_rotldi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3939 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    /* (SZ - cnt) % SZ == -cnt % SZ */
    if (CONST_INT_P (operands[2]))
      {
        operands[2] = GEN_INT ((-INTVAL (operands[2]))
			       & (GET_MODE_BITSIZE (DImode) - 1));
        if (operands[2] == const0_rtx)
          {
	    emit_insn (gen_movdi (operands[0], operands[1]));
	    DONE;
          }
      }
    else
      operands[2] = expand_simple_unop (QImode, NEG, operands[2],
					NULL_RTX, 1);
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_ROTATERT (DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:3990 */
extern rtx_insn *gen_split_25 (rtx_insn *, rtx *);
rtx_insn *
gen_split_25 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_25\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4000 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    operands[3] = gen_lowpart (QImode, operands[0]);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand2),
	42)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		copy_rtx (operand3)),
	44)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4005 */
extern rtx_insn *gen_split_26 (rtx_insn *, rtx *);
rtx_insn *
gen_split_26 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_26\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4015 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    operands[3] = gen_lowpart (QImode, operands[0]);
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand2),
	42)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		copy_rtx (operand3)),
	60)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4037 */
extern rtx_insn *gen_split_27 (rtx_insn *, rtx *);
rtx_insn *
gen_split_27 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_27\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4047 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  operands[3] = gen_lowpart (QImode, operands[0]);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand2),
	42)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DImode,
	gen_rtvec (2,
		operand1,
		copy_rtx (operand3)),
	43)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4052 */
extern rtx_insn *gen_split_28 (rtx_insn *, rtx *);
rtx_insn *
gen_split_28 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_28\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4062 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  operands[3] = gen_lowpart (QImode, operands[0]);
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit_insn (gen_rtx_SET (operand3,
	gen_rtx_UNSPEC (QImode,
	gen_rtvec (1,
		operand2),
	42)));
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SImode,
	gen_rtvec (2,
		operand1,
		copy_rtx (operand3)),
	45)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4282 */
rtx
gen_extv (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTRACT (DImode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4282 */
rtx
gen_extzv (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  return gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTRACT (DImode,
	operand1,
	operand2,
	operand3));
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4302 */
rtx
gen_insvsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4308 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  unsigned HOST_WIDE_INT width = UINTVAL (operands[1]);
  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
  rtx value = operands[3];

  if (width == 0 || (pos + width) > GET_MODE_BITSIZE (SImode))
    FAIL;

  if (CONST_INT_P (value))
    {
      unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;

      /* Prefer AND/OR for inserting all zeros or all ones.  */
      if ((UINTVAL (value) & mask) == 0
	   || (UINTVAL (value) & mask) == mask)
	FAIL;

      /* 16-bit aligned 16-bit wide insert is handled by insv_imm.  */
      if (width == 16 && (pos % 16) == 0)
	DONE;
    }
  operands[3] = force_reg (SImode, value);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (SImode,
	operand0,
	operand1,
	operand2),
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4302 */
rtx
gen_insvdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4308 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  unsigned HOST_WIDE_INT width = UINTVAL (operands[1]);
  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
  rtx value = operands[3];

  if (width == 0 || (pos + width) > GET_MODE_BITSIZE (DImode))
    FAIL;

  if (CONST_INT_P (value))
    {
      unsigned HOST_WIDE_INT mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;

      /* Prefer AND/OR for inserting all zeros or all ones.  */
      if ((UINTVAL (value) & mask) == 0
	   || (UINTVAL (value) & mask) == mask)
	FAIL;

      /* 16-bit aligned 16-bit wide insert is handled by insv_imm.  */
      if (width == 16 && (pos % 16) == 0)
	DONE;
    }
  operands[3] = force_reg (DImode, value);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit_insn (gen_rtx_SET (gen_rtx_ZERO_EXTRACT (DImode,
	operand0,
	operand1,
	operand2),
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4765 */
rtx
gen_divhf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4770 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (HFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (HFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4765 */
rtx
gen_divsf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4770 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (SFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4765 */
rtx
gen_divdf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4770 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (DFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (DFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4794 */
rtx
gen_sqrthf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrthf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4798 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4794 */
rtx
gen_sqrtsf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtsf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4798 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4794 */
rtx
gen_sqrtdf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtdf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4798 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (DFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4864 */
rtx
gen_copysigndf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysigndf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4869 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx mask = gen_reg_rtx (DImode);
  emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 63));
  emit_insn (gen_aarch64_simd_bsldf (operands[0], mask,
				     operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4881 */
rtx
gen_copysignsf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL _Pragma ("GCC error \"copysignsf3 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4886 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx mask = gen_reg_rtx (DImode);

  /* Juggle modes to get us in to a vector mode for BSL.  */
  rtx op1 = lowpart_subreg (V2SFmode, operands[1], SFmode);
  rtx op2 = lowpart_subreg (V2SFmode, operands[2], SFmode);
  rtx tmp = gen_reg_rtx (V2SFmode);
  emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 31));
  emit_insn (gen_aarch64_simd_bslv2sf (tmp, mask, op2, op1));
  emit_move_insn (operands[0], lowpart_subreg (SFmode, tmp, V2SFmode));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4905 */
rtx
gen_aarch64_reload_movcpsfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4910 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4905 */
rtx
gen_aarch64_reload_movcpsfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4910 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4905 */
rtx
gen_aarch64_reload_movcpdfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4910 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (DFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (DFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4905 */
rtx
gen_aarch64_reload_movcpdfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4910 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (DFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (DFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4905 */
rtx
gen_aarch64_reload_movcptfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4910 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (TFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (TFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4905 */
rtx
gen_aarch64_reload_movcptfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4910 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (TFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (TFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv8qisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V8QImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V8QImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv16qisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V16QImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V16QImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv4hisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4HImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4HImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv8hisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V8HImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V8HImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv2sisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2SImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2SImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv4sisi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4SImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4SImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv2disi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2DImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2DImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv2sfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv4sfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv2dfsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2DFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2DFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv8qidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V8QImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V8QImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv16qidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V16QImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V16QImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv4hidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4HImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4HImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv8hidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V8HImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V8HImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv2sidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2SImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2SImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv4sidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4SImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4SImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv2didi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2DImode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2DImode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv2sfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv4sfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V4SFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V4SFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4918 */
rtx
gen_aarch64_reload_movcpv2dfdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4923 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
   aarch64_expand_mov_immediate (operands[2], XEXP (operands[1], 0));
   emit_move_insn (operands[0], gen_rtx_MEM (V2DFmode, operands[2]));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_MEM (V2DFmode,
	operand1)));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4930 */
rtx
gen_aarch64_reload_movti (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4936 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx op0 = simplify_gen_subreg (TImode, operands[0], TImode, 0);
    rtx op1 = simplify_gen_subreg (TImode, operands[1], TImode, 0);
    gen_aarch64_movtilow_tilow (op0, op1);
    gen_aarch64_movdi_tihigh (operands[2], op1);
    gen_aarch64_movtihigh_di (op0, operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:4930 */
rtx
gen_aarch64_reload_movtf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4936 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
    rtx op0 = simplify_gen_subreg (TImode, operands[0], TFmode, 0);
    rtx op1 = simplify_gen_subreg (TImode, operands[1], TFmode, 0);
    gen_aarch64_movtilow_tilow (op0, op1);
    gen_aarch64_movdi_tihigh (operands[2], op1);
    gen_aarch64_movtihigh_di (op0, operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  emit_insn (gen_rtx_CLOBBER (VOIDmode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5004 */
rtx
gen_add_losym (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5009 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  machine_mode mode = GET_MODE (operands[0]);

  emit_insn ((mode == DImode
	      ? gen_add_losym_di
	      : gen_add_losym_si) (operands[0],
				   operands[1],
				   operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_LO_SUM (VOIDmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5095 */
rtx
gen_tlsgd_small (rtx operand0,
	rtx operand1)
{
  rtx operand2;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5101 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  operands[2] = aarch64_tls_get_addr ();
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (3,
		gen_rtx_SET (operand0,
	gen_rtx_CALL (VOIDmode,
	gen_rtx_MEM (DImode,
	operand2),
	const1_rtx)),
		gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		operand1),
	24),
		gen_hard_reg_clobber (DImode, 30))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5249 */
rtx
gen_get_thread_pointerdi (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5252 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx tmp = aarch64_load_tp (operands[0]);
  if (tmp != operands[0])
    emit_move_insn (operands[0], tmp);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit (operand0, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5260 */
rtx
gen_stack_protect_set (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5264 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  machine_mode mode = GET_MODE (operands[0]);

  emit_insn ((mode == DImode
	      ? gen_stack_protect_set_di
	      : gen_stack_protect_set_si) (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5283 */
rtx
gen_stack_protect_test (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5288 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx result;
  machine_mode mode = GET_MODE (operands[0]);

  result = gen_reg_rtx(mode);

  emit_insn ((mode == DImode
	      ? gen_stack_protect_test_di
	      : gen_stack_protect_test_si) (result,
					    operands[0],
					    operands[1]));

  if (mode == DImode)
    emit_jump_insn (gen_cbranchdi4 (gen_rtx_EQ (VOIDmode, result, const0_rtx),
				    result, const0_rtx, operands[2]));
  else
    emit_jump_insn (gen_cbranchsi4 (gen_rtx_EQ (VOIDmode, result, const0_rtx),
				    result, const0_rtx, operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md:5353 */
rtx
gen_doloop_end (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5357 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64.md"
{
  rtx s0;
  rtx bcomp;
  rtx loc_ref;
  rtx cc_reg;
  rtx insn;
  rtx cmp;

  /* Currently SMS relies on the do-loop pattern to recognize loops
     where (1) the control part consists of all insns defining and/or
     using a certain 'count' register and (2) the loop count can be
     adjusted by modifying this register prior to the loop.
     ??? The possible introduction of a new block to initialize the
     new IV can potentially affect branch optimizations.  */

  if (GET_MODE (operands[0]) != DImode)
    FAIL;

  s0 = operands [0];
  insn = emit_insn (gen_adddi3_compare0 (s0, s0, GEN_INT (-1)));

  cmp = XVECEXP (PATTERN (insn), 0, 0);
  cc_reg = SET_DEST (cmp);
  bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
  loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
  emit_jump_insn (gen_rtx_SET (pc_rtx,
			       gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
						     loc_ref, pc_rtx)));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_USE (VOIDmode,
	operand0));
  emit_insn (gen_rtx_USE (VOIDmode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V8QImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V16QImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V4HImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V8HImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V2SImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V4SImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V2DImode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V4HFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V8HFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V2SFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V4SFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:21 */
rtx
gen_movv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 25 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"

    if (GET_CODE (operands[0]) == MEM)
      operands[1] = force_reg (V2DFmode, operands[1]);
  
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V8QImode)
      && !register_operand (operands[1], V8QImode))
    operands[1] = force_reg (V8QImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V16QImode)
      && !register_operand (operands[1], V16QImode))
    operands[1] = force_reg (V16QImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V4HImode)
      && !register_operand (operands[1], V4HImode))
    operands[1] = force_reg (V4HImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V8HImode)
      && !register_operand (operands[1], V8HImode))
    operands[1] = force_reg (V8HImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V2SImode)
      && !register_operand (operands[1], V2SImode))
    operands[1] = force_reg (V2SImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V4SImode)
      && !register_operand (operands[1], V4SImode))
    operands[1] = force_reg (V4SImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V2DImode)
      && !register_operand (operands[1], V2DImode))
    operands[1] = force_reg (V2DImode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V2SFmode)
      && !register_operand (operands[1], V2SFmode))
    operands[1] = force_reg (V2SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V4SFmode)
      && !register_operand (operands[1], V4SFmode))
    operands[1] = force_reg (V4SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:31 */
rtx
gen_movmisalignv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 35 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* This pattern is not permitted to fail during expansion: if both arguments
     are non-registers (e.g. memory := constant, which can be created by the
     auto-vectorizer), force operand 1 into a register.  */
  if (!register_operand (operands[0], V2DFmode)
      && !register_operand (operands[1], V2DFmode))
    operands[1] = force_reg (V2DFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:184 */
extern rtx_insn *gen_split_29 (rtx_insn *, rtx *);
rtx_insn *
gen_split_29 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_29\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:184 */
extern rtx_insn *gen_split_30 (rtx_insn *, rtx *);
rtx_insn *
gen_split_30 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_30\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:184 */
extern rtx_insn *gen_split_31 (rtx_insn *, rtx *);
rtx_insn *
gen_split_31 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_31\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:184 */
extern rtx_insn *gen_split_32 (rtx_insn *, rtx *);
rtx_insn *
gen_split_32 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_32\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:184 */
extern rtx_insn *gen_split_33 (rtx_insn *, rtx *);
rtx_insn *
gen_split_33 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_33\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:184 */
extern rtx_insn *gen_split_34 (rtx_insn *, rtx *);
rtx_insn *
gen_split_34 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_34\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:184 */
extern rtx_insn *gen_split_35 (rtx_insn *, rtx *);
rtx_insn *
gen_split_35 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_35\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 191 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, DImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:196 */
extern rtx_insn *gen_split_36 (rtx_insn *, rtx *);
rtx_insn *
gen_split_36 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_36\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 203 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:196 */
extern rtx_insn *gen_split_37 (rtx_insn *, rtx *);
rtx_insn *
gen_split_37 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_37\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 203 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:196 */
extern rtx_insn *gen_split_38 (rtx_insn *, rtx *);
rtx_insn *
gen_split_38 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_38\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 203 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:196 */
extern rtx_insn *gen_split_39 (rtx_insn *, rtx *);
rtx_insn *
gen_split_39 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_39\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 203 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:196 */
extern rtx_insn *gen_split_40 (rtx_insn *, rtx *);
rtx_insn *
gen_split_40 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_40\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 203 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:196 */
extern rtx_insn *gen_split_41 (rtx_insn *, rtx *);
rtx_insn *
gen_split_41 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_41\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 203 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:196 */
extern rtx_insn *gen_split_42 (rtx_insn *, rtx *);
rtx_insn *
gen_split_42 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_42\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 203 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_simd_move (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_aarch64_split_simd_movv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 212 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V8QImode, src);
        rtx src_high_part = gen_highpart (V8QImode, src);

        emit_insn
          (gen_move_lo_quad_v16qi (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v16qi (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V8QImode, dst);
        rtx dst_high_part = gen_highpart (V8QImode, dst);
        rtx lo = aarch64_simd_vect_par_cnst_half (V16QImode, false);
        rtx hi = aarch64_simd_vect_par_cnst_half (V16QImode, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v16qilow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v16qihigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_aarch64_split_simd_movv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 212 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V4HImode, src);
        rtx src_high_part = gen_highpart (V4HImode, src);

        emit_insn
          (gen_move_lo_quad_v8hi (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v8hi (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V4HImode, dst);
        rtx dst_high_part = gen_highpart (V4HImode, dst);
        rtx lo = aarch64_simd_vect_par_cnst_half (V8HImode, false);
        rtx hi = aarch64_simd_vect_par_cnst_half (V8HImode, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v8hilow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v8hihigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_aarch64_split_simd_movv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 212 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V2SImode, src);
        rtx src_high_part = gen_highpart (V2SImode, src);

        emit_insn
          (gen_move_lo_quad_v4si (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v4si (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V2SImode, dst);
        rtx dst_high_part = gen_highpart (V2SImode, dst);
        rtx lo = aarch64_simd_vect_par_cnst_half (V4SImode, false);
        rtx hi = aarch64_simd_vect_par_cnst_half (V4SImode, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v4silow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v4sihigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_aarch64_split_simd_movv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 212 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (DImode, src);
        rtx src_high_part = gen_highpart (DImode, src);

        emit_insn
          (gen_move_lo_quad_v2di (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v2di (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (DImode, dst);
        rtx dst_high_part = gen_highpart (DImode, dst);
        rtx lo = aarch64_simd_vect_par_cnst_half (V2DImode, false);
        rtx hi = aarch64_simd_vect_par_cnst_half (V2DImode, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v2dilow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v2dihigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_aarch64_split_simd_movv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 212 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V4HFmode, src);
        rtx src_high_part = gen_highpart (V4HFmode, src);

        emit_insn
          (gen_move_lo_quad_v8hf (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v8hf (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V4HFmode, dst);
        rtx dst_high_part = gen_highpart (V4HFmode, dst);
        rtx lo = aarch64_simd_vect_par_cnst_half (V8HFmode, false);
        rtx hi = aarch64_simd_vect_par_cnst_half (V8HFmode, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v8hflow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v8hfhigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_aarch64_split_simd_movv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 212 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (V2SFmode, src);
        rtx src_high_part = gen_highpart (V2SFmode, src);

        emit_insn
          (gen_move_lo_quad_v4sf (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v4sf (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (V2SFmode, dst);
        rtx dst_high_part = gen_highpart (V2SFmode, dst);
        rtx lo = aarch64_simd_vect_par_cnst_half (V4SFmode, false);
        rtx hi = aarch64_simd_vect_par_cnst_half (V4SFmode, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v4sflow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v4sfhigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:208 */
rtx
gen_aarch64_split_simd_movv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 212 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx dst = operands[0];
    rtx src = operands[1];

    if (GP_REGNUM_P (REGNO (src)))
      {
        rtx src_low_part = gen_lowpart (DFmode, src);
        rtx src_high_part = gen_highpart (DFmode, src);

        emit_insn
          (gen_move_lo_quad_v2df (dst, src_low_part));
        emit_insn
          (gen_move_hi_quad_v2df (dst, src_high_part));
      }

    else
      {
        rtx dst_low_part = gen_lowpart (DFmode, dst);
        rtx dst_high_part = gen_highpart (DFmode, dst);
        rtx lo = aarch64_simd_vect_par_cnst_half (V2DFmode, false);
        rtx hi = aarch64_simd_vect_par_cnst_half (V2DFmode, true);

        emit_insn
          (gen_aarch64_simd_mov_from_v2dflow (dst_low_part, src, lo));
        emit_insn
          (gen_aarch64_simd_mov_from_v2dfhigh (dst_high_part, src, hi));
      }
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:327 */
rtx
gen_ctzv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ctzv2si2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
     emit_insn (gen_bswapv2si2 (operands[0], operands[1]));
     rtx op0_castsi2qi = simplify_gen_subreg(V8QImode, operands[0],
					     V2SImode, 0);
     emit_insn (gen_aarch64_rbitv8qi (op0_castsi2qi, op0_castsi2qi));
     emit_insn (gen_clzv2si2 (operands[0], operands[0]));
     DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_CTZ (V2SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:327 */
rtx
gen_ctzv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"ctzv4si2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 331 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
     emit_insn (gen_bswapv4si2 (operands[0], operands[1]));
     rtx op0_castsi2qi = simplify_gen_subreg(V16QImode, operands[0],
					     V4SImode, 0);
     emit_insn (gen_aarch64_rbitv16qi (op0_castsi2qi, op0_castsi2qi));
     emit_insn (gen_clzv4si2 (operands[0], operands[0]));
     DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_CTZ (V4SImode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:402 */
rtx
gen_rsqrtv2sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtv2sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 407 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	64)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:402 */
rtx
gen_rsqrtv4sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtv4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 407 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	64)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:402 */
rtx
gen_rsqrtv2df2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtv2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 407 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	64)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:402 */
rtx
gen_rsqrtsf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtsf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 407 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (SFmode,
	gen_rtvec (1,
		operand1),
	64)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:402 */
rtx
gen_rsqrtdf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"rsqrtdf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 407 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_emit_approx_sqrt (operands[0], operands[1], true);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		operand1),
	64)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:648 */
rtx
gen_ashlv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 653 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8QImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv8qi (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V8QImode);
      emit_insn (gen_aarch64_simd_dupv8qi (tmp,
					     convert_to_mode (QImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv8qi (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:648 */
rtx
gen_ashlv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 653 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V16QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V16QImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv16qi (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V16QImode);
      emit_insn (gen_aarch64_simd_dupv16qi (tmp,
					     convert_to_mode (QImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv16qi (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:648 */
rtx
gen_ashlv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 653 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4HImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv4hi (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V4HImode);
      emit_insn (gen_aarch64_simd_dupv4hi (tmp,
					     convert_to_mode (HImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv4hi (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:648 */
rtx
gen_ashlv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 653 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8HImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv8hi (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V8HImode);
      emit_insn (gen_aarch64_simd_dupv8hi (tmp,
					     convert_to_mode (HImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv8hi (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:648 */
rtx
gen_ashlv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 653 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2SImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv2si (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V2SImode);
      emit_insn (gen_aarch64_simd_dupv2si (tmp,
					     convert_to_mode (SImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv2si (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:648 */
rtx
gen_ashlv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 653 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4SImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv4si (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V4SImode);
      emit_insn (gen_aarch64_simd_dupv4si (tmp,
					     convert_to_mode (SImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv4si (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:648 */
rtx
gen_ashlv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 653 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2DImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount >= 0 && shift_amount < bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2DImode,
						       shift_amount);
	  emit_insn (gen_aarch64_simd_imm_shlv2di (operands[0],
						     operands[1],
						     tmp));
          DONE;
        }
      else
        {
          operands[2] = force_reg (SImode, operands[2]);
        }
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (V2DImode);
      emit_insn (gen_aarch64_simd_dupv2di (tmp,
					     convert_to_mode (DImode,
							      operands[2],
							      0)));
      emit_insn (gen_aarch64_simd_reg_sshlv2di (operands[0], operands[1],
						  tmp));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:695 */
rtx
gen_lshrv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 700 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8QImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv8qi (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V8QImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv8qi (tmp1,
					     convert_to_mode (QImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv8qi_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:695 */
rtx
gen_lshrv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 700 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V16QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V16QImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv16qi (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V16QImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv16qi (tmp1,
					     convert_to_mode (QImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv16qi_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:695 */
rtx
gen_lshrv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 700 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4HImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv4hi (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V4HImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv4hi (tmp1,
					     convert_to_mode (HImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv4hi_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:695 */
rtx
gen_lshrv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 700 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8HImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv8hi (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V8HImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv8hi (tmp1,
					     convert_to_mode (HImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv8hi_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:695 */
rtx
gen_lshrv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 700 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2SImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv2si (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V2SImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv2si (tmp1,
					     convert_to_mode (SImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv2si_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:695 */
rtx
gen_lshrv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 700 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4SImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv4si (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V4SImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv4si (tmp1,
					     convert_to_mode (SImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv4si_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:695 */
rtx
gen_lshrv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 700 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2DImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2DImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_lshrv2di (operands[0],
						  operands[1],
						  tmp));
	  DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V2DImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv2di (tmp1,
					     convert_to_mode (DImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv2di_unsigned (operands[0],
							  operands[1],
							  tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:742 */
rtx
gen_ashrv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 747 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8QImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv8qi (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V8QImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv8qi (tmp1,
					     convert_to_mode (QImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv8qi_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:742 */
rtx
gen_ashrv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 747 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V16QImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V16QImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv16qi (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V16QImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv16qi (tmp1,
					     convert_to_mode (QImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv16qi_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:742 */
rtx
gen_ashrv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 747 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4HImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv4hi (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V4HImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv4hi (tmp1,
					     convert_to_mode (HImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv4hi_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:742 */
rtx
gen_ashrv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 747 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V8HImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V8HImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv8hi (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V8HImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv8hi (tmp1,
					     convert_to_mode (HImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv8hi_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:742 */
rtx
gen_ashrv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 747 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2SImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv2si (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V2SImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv2si (tmp1,
					     convert_to_mode (SImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv2si_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:742 */
rtx
gen_ashrv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 747 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V4SImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V4SImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv4si (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V4SImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv4si (tmp1,
					     convert_to_mode (SImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv4si_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:742 */
rtx
gen_ashrv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 747 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int bit_width = GET_MODE_UNIT_SIZE (V2DImode) * BITS_PER_UNIT;
  int shift_amount;

  if (CONST_INT_P (operands[2]))
    {
      shift_amount = INTVAL (operands[2]);
      if (shift_amount > 0 && shift_amount <= bit_width)
        {
	  rtx tmp = aarch64_simd_gen_const_vector_dup (V2DImode,
						       shift_amount);
          emit_insn (gen_aarch64_simd_ashrv2di (operands[0],
						  operands[1],
						  tmp));
          DONE;
	}
      else
        operands[2] = force_reg (SImode, operands[2]);
    }
  else if (MEM_P (operands[2]))
    {
      operands[2] = force_reg (SImode, operands[2]);
    }

  if (REG_P (operands[2]))
    {
      rtx tmp = gen_reg_rtx (SImode);
      rtx tmp1 = gen_reg_rtx (V2DImode);
      emit_insn (gen_negsi2 (tmp, operands[2]));
      emit_insn (gen_aarch64_simd_dupv2di (tmp1,
					     convert_to_mode (DImode,
							      tmp, 0)));
      emit_insn (gen_aarch64_simd_reg_shlv2di_signed (operands[0],
							operands[1],
							tmp1));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:789 */
rtx
gen_vashlv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 794 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv8qi (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:789 */
rtx
gen_vashlv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 794 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv16qi (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:789 */
rtx
gen_vashlv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 794 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv4hi (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:789 */
rtx
gen_vashlv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 794 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv8hi (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:789 */
rtx
gen_vashlv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 794 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv2si (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:789 */
rtx
gen_vashlv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 794 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv4si (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:789 */
rtx
gen_vashlv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 794 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_simd_reg_sshlv2di (operands[0], operands[1],
					      operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:803 */
rtx
gen_vashrv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 808 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V8QImode);
  emit (gen_negv8qi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv8qi_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:803 */
rtx
gen_vashrv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 808 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V16QImode);
  emit (gen_negv16qi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv16qi_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:803 */
rtx
gen_vashrv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 808 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V4HImode);
  emit (gen_negv4hi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv4hi_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:803 */
rtx
gen_vashrv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 808 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V8HImode);
  emit (gen_negv8hi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv8hi_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:803 */
rtx
gen_vashrv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 808 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V2SImode);
  emit (gen_negv2si2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv2si_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:803 */
rtx
gen_vashrv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 808 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V4SImode);
  emit (gen_negv4si2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv4si_signed (operands[0], operands[1],
						    neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:817 */
rtx
gen_aarch64_ashr_simddi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 822 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* An arithmetic shift right by 64 fills the result with copies of the sign
       bit, just like asr by 63 - however the standard pattern does not handle
       a shift by 64.  */
    if (INTVAL (operands[2]) == 64)
      operands[2] = GEN_INT (63);
    emit_insn (gen_ashrdi3 (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:833 */
rtx
gen_vlshrv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 838 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V8QImode);
  emit (gen_negv8qi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv8qi_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:833 */
rtx
gen_vlshrv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 838 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V16QImode);
  emit (gen_negv16qi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv16qi_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:833 */
rtx
gen_vlshrv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 838 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V4HImode);
  emit (gen_negv4hi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv4hi_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:833 */
rtx
gen_vlshrv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 838 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V8HImode);
  emit (gen_negv8hi2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv8hi_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:833 */
rtx
gen_vlshrv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 838 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V2SImode);
  emit (gen_negv2si2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv2si_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:833 */
rtx
gen_vlshrv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 838 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx neg = gen_reg_rtx (V4SImode);
  emit (gen_negv4si2 (neg, operands[2]));
  emit_insn (gen_aarch64_simd_reg_shlv4si_unsigned (operands[0], operands[1],
						      neg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:846 */
rtx
gen_aarch64_lshr_simddi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 851 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    if (INTVAL (operands[2]) == 64)
      emit_move_insn (operands[0], const0_rtx);
    else
      emit_insn (gen_lshrdi3 (operands[0], operands[1], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:860 */
rtx
gen_vec_setv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 865 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv8qi (operands[0], operands[1],
					    GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:860 */
rtx
gen_vec_setv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 865 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv16qi (operands[0], operands[1],
					    GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:860 */
rtx
gen_vec_setv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 865 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv4hi (operands[0], operands[1],
					    GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:860 */
rtx
gen_vec_setv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 865 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv8hi (operands[0], operands[1],
					    GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:860 */
rtx
gen_vec_setv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 865 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv2si (operands[0], operands[1],
					    GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:860 */
rtx
gen_vec_setv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 865 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv4si (operands[0], operands[1],
					    GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:913 */
rtx
gen_vec_setv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 918 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv2di (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:943 */
rtx
gen_vec_setv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 948 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv4hf (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:943 */
rtx
gen_vec_setv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 948 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv8hf (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:943 */
rtx
gen_vec_setv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 948 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv2sf (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:943 */
rtx
gen_vec_setv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 948 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv4sf (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:943 */
rtx
gen_vec_setv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 948 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << INTVAL (operands[2]);
    emit_insn (gen_aarch64_simd_vec_setv2df (operands[0], operands[1],
					  GEN_INT (elem), operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1062 */
rtx
gen_smaxv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1067 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  enum rtx_code cmp_operator;
  rtx cmp_fmt;

  switch (SMAX)
    {
    case UMIN:
      cmp_operator = LTU;
      break;
    case SMIN:
      cmp_operator = LT;
      break;
    case UMAX:
      cmp_operator = GTU;
      break;
    case SMAX:
      cmp_operator = GT;
      break;
    default:
      gcc_unreachable ();
    }

  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
  emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
              operands[2], cmp_fmt, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SMAX (V2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1062 */
rtx
gen_sminv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1067 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  enum rtx_code cmp_operator;
  rtx cmp_fmt;

  switch (SMIN)
    {
    case UMIN:
      cmp_operator = LTU;
      break;
    case SMIN:
      cmp_operator = LT;
      break;
    case UMAX:
      cmp_operator = GTU;
      break;
    case SMAX:
      cmp_operator = GT;
      break;
    default:
      gcc_unreachable ();
    }

  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
  emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
              operands[2], cmp_fmt, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SMIN (V2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1062 */
rtx
gen_umaxv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1067 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  enum rtx_code cmp_operator;
  rtx cmp_fmt;

  switch (UMAX)
    {
    case UMIN:
      cmp_operator = LTU;
      break;
    case SMIN:
      cmp_operator = LT;
      break;
    case UMAX:
      cmp_operator = GTU;
      break;
    case SMAX:
      cmp_operator = GT;
      break;
    default:
      gcc_unreachable ();
    }

  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
  emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
              operands[2], cmp_fmt, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UMAX (V2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1062 */
rtx
gen_uminv2di3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1067 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  enum rtx_code cmp_operator;
  rtx cmp_fmt;

  switch (UMIN)
    {
    case UMIN:
      cmp_operator = LTU;
      break;
    case SMIN:
      cmp_operator = LT;
      break;
    case UMAX:
      cmp_operator = GTU;
      break;
    case SMAX:
      cmp_operator = GT;
      break;
    default:
      gcc_unreachable ();
    }

  cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
  emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
              operands[2], cmp_fmt, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UMIN (V2DImode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1191 */
rtx
gen_move_lo_quad_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1195 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v16qi (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1191 */
rtx
gen_move_lo_quad_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1195 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v8hi (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1191 */
rtx
gen_move_lo_quad_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1195 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v4si (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1191 */
rtx
gen_move_lo_quad_v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1195 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v2di (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1191 */
rtx
gen_move_lo_quad_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1195 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v8hf (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1191 */
rtx
gen_move_lo_quad_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1195 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v4sf (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1191 */
rtx
gen_move_lo_quad_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1195 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_move_lo_quad_internal_be_v2df (operands[0], operands[1]));
  else
    emit_insn (gen_move_lo_quad_internal_v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1237 */
rtx
gen_move_hi_quad_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1241 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v16qi (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v16qi (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1237 */
rtx
gen_move_hi_quad_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1241 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v8hi (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v8hi (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1237 */
rtx
gen_move_hi_quad_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1241 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v4si (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v4si (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1237 */
rtx
gen_move_hi_quad_v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1241 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V2DImode, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v2di (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v2di (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1237 */
rtx
gen_move_hi_quad_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1241 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HFmode, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v8hf (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v8hf (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1237 */
rtx
gen_move_hi_quad_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1241 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SFmode, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v4sf (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v4sf (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1237 */
rtx
gen_move_hi_quad_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1241 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V2DFmode, false);
  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_simd_move_hi_quad_be_v2df (operands[0],
		    operands[1], p));
  else
    emit_insn (gen_aarch64_simd_move_hi_quad_v2df (operands[0],
		    operands[1], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1263 */
rtx
gen_vec_pack_trunc_v4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1268 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx tempreg = gen_reg_rtx (V8HImode);
  int lo = BYTES_BIG_ENDIAN ? 2 : 1;
  int hi = BYTES_BIG_ENDIAN ? 1 : 2;

  emit_insn (gen_move_lo_quad_v8hi (tempreg, operands[lo]));
  emit_insn (gen_move_hi_quad_v8hi (tempreg, operands[hi]));
  emit_insn (gen_aarch64_simd_vec_pack_trunc_v8hi (operands[0], tempreg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1263 */
rtx
gen_vec_pack_trunc_v2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1268 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx tempreg = gen_reg_rtx (V4SImode);
  int lo = BYTES_BIG_ENDIAN ? 2 : 1;
  int hi = BYTES_BIG_ENDIAN ? 1 : 2;

  emit_insn (gen_move_lo_quad_v4si (tempreg, operands[lo]));
  emit_insn (gen_move_hi_quad_v4si (tempreg, operands[hi]));
  emit_insn (gen_aarch64_simd_vec_pack_trunc_v4si (operands[0], tempreg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1263 */
rtx
gen_vec_pack_trunc_di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1268 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx tempreg = gen_reg_rtx (V2DImode);
  int lo = BYTES_BIG_ENDIAN ? 2 : 1;
  int hi = BYTES_BIG_ENDIAN ? 1 : 2;

  emit_insn (gen_move_lo_quad_v2di (tempreg, operands[lo]));
  emit_insn (gen_move_hi_quad_v2di (tempreg, operands[hi]));
  emit_insn (gen_aarch64_simd_vec_pack_trunc_v2di (operands[0], tempreg));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1321 */
rtx
gen_vec_unpacks_hi_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1325 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_hi_v16qi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1321 */
rtx
gen_vec_unpacku_hi_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1325 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
    emit_insn (gen_aarch64_simd_vec_unpacku_hi_v16qi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1321 */
rtx
gen_vec_unpacks_hi_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1325 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_hi_v8hi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1321 */
rtx
gen_vec_unpacku_hi_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1325 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
    emit_insn (gen_aarch64_simd_vec_unpacku_hi_v8hi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1321 */
rtx
gen_vec_unpacks_hi_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1325 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_hi_v4si (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1321 */
rtx
gen_vec_unpacku_hi_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1325 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
    emit_insn (gen_aarch64_simd_vec_unpacku_hi_v4si (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1333 */
rtx
gen_vec_unpacks_lo_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1337 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v16qi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1333 */
rtx
gen_vec_unpacku_lo_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1337 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, false);
    emit_insn (gen_aarch64_simd_vec_unpacku_lo_v16qi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1333 */
rtx
gen_vec_unpacks_lo_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1337 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v8hi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1333 */
rtx
gen_vec_unpacku_lo_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1337 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, false);
    emit_insn (gen_aarch64_simd_vec_unpacku_lo_v8hi (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1333 */
rtx
gen_vec_unpacks_lo_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1337 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v4si (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1333 */
rtx
gen_vec_unpacku_lo_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1337 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, false);
    emit_insn (gen_aarch64_simd_vec_unpacku_lo_v4si (operands[0],
							  operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1452 */
rtx
gen_vec_widen_smult_lo_v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1457 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, false);
   emit_insn (gen_aarch64_simd_vec_smult_lo_v16qi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1452 */
rtx
gen_vec_widen_umult_lo_v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1457 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, false);
   emit_insn (gen_aarch64_simd_vec_umult_lo_v16qi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1452 */
rtx
gen_vec_widen_smult_lo_v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1457 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, false);
   emit_insn (gen_aarch64_simd_vec_smult_lo_v8hi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1452 */
rtx
gen_vec_widen_umult_lo_v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1457 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, false);
   emit_insn (gen_aarch64_simd_vec_umult_lo_v8hi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1452 */
rtx
gen_vec_widen_smult_lo_v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1457 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, false);
   emit_insn (gen_aarch64_simd_vec_smult_lo_v4si (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1452 */
rtx
gen_vec_widen_umult_lo_v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1457 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, false);
   emit_insn (gen_aarch64_simd_vec_umult_lo_v4si (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;
 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1479 */
rtx
gen_vec_widen_smult_hi_v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1484 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
   emit_insn (gen_aarch64_simd_vec_smult_hi_v16qi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V8HImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1479 */
rtx
gen_vec_widen_umult_hi_v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1484 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
   emit_insn (gen_aarch64_simd_vec_umult_hi_v16qi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V8HImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1479 */
rtx
gen_vec_widen_smult_hi_v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1484 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
   emit_insn (gen_aarch64_simd_vec_smult_hi_v8hi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V4SImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1479 */
rtx
gen_vec_widen_umult_hi_v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1484 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
   emit_insn (gen_aarch64_simd_vec_umult_hi_v8hi (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V4SImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1479 */
rtx
gen_vec_widen_smult_hi_v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1484 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
   emit_insn (gen_aarch64_simd_vec_smult_hi_v4si (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand1));
  emit_insn (gen_rtx_SIGN_EXTEND (V2DImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1479 */
rtx
gen_vec_widen_umult_hi_v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1484 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
   rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
   emit_insn (gen_aarch64_simd_vec_umult_hi_v4si (operands[0],
						       operands[1],
						       operands[2], p));
   DONE;

 }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand1));
  emit_insn (gen_rtx_ZERO_EXTEND (V2DImode,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1546 */
rtx
gen_divv4hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1551 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V4HFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V4HFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1546 */
rtx
gen_divv8hf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1551 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V8HFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V8HFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1546 */
rtx
gen_divv2sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1551 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V2SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V2SFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1546 */
rtx
gen_divv4sf3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1551 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V4SFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V4SFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1546 */
rtx
gen_divv2df3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1551 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_div (operands[0], operands[1], operands[2]))
    DONE;

  operands[1] = force_reg (V2DFmode, operands[1]);
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_DIV (V2DFmode,
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixv4hfv4hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixunsv4hfv4hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixv8hfv8hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixunsv8hfv8hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixv2sfv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixunsv2sfv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixv4sfv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixunsv4sfv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixv2dfv2di2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1804 */
rtx
gen_fixunsv2dfv2di2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1810 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fix_truncv4hfv4hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fixuns_truncv4hfv4hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4HImode,
	gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fix_truncv8hfv8hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fixuns_truncv8hfv8hi2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V8HImode,
	gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fix_truncv2sfv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fixuns_truncv2sfv2si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2SImode,
	gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fix_truncv4sfv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fixuns_truncv4sfv4si2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V4SImode,
	gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fix_truncv2dfv2di2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1812 */
rtx
gen_fixuns_truncv2dfv2di2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1818 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSIGNED_FIX (V2DImode,
	gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	21))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1820 */
rtx
gen_ftruncv4hf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1825 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	21)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1820 */
rtx
gen_ftruncv8hf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1825 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	21)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1820 */
rtx
gen_ftruncv2sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1825 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	21)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1820 */
rtx
gen_ftruncv4sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1825 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	21)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1820 */
rtx
gen_ftruncv2df2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1825 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	21)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1886 */
rtx
gen_vec_unpacks_lo_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1890 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HFmode, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v8hf (operands[0],
						       operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1886 */
rtx
gen_vec_unpacks_lo_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1890 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SFmode, false);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v4sf (operands[0],
						       operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1909 */
rtx
gen_vec_unpacks_hi_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1913 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HFmode, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v8hf (operands[0],
						       operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1909 */
rtx
gen_vec_unpacks_hi_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1913 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SFmode, true);
    emit_insn (gen_aarch64_simd_vec_unpacks_lo_v4sf (operands[0],
						       operands[1], p));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1962 */
rtx
gen_aarch64_float_truncate_hi_v4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1967 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx (*gen) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN
			     ? gen_aarch64_float_truncate_hi_v4sf_be
			     : gen_aarch64_float_truncate_hi_v4sf_le;
  emit_insn (gen (operands[0], operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1962 */
rtx
gen_aarch64_float_truncate_hi_v8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1967 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx (*gen) (rtx, rtx, rtx) = BYTES_BIG_ENDIAN
			     ? gen_aarch64_float_truncate_hi_v8hf_be
			     : gen_aarch64_float_truncate_hi_v8hf_le;
  emit_insn (gen (operands[0], operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1976 */
rtx
gen_vec_pack_trunc_v2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 1985 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx tmp = gen_reg_rtx (V2SFmode);
    int lo = BYTES_BIG_ENDIAN ? 2 : 1;
    int hi = BYTES_BIG_ENDIAN ? 1 : 2;

    emit_insn (gen_aarch64_float_truncate_lo_v2sf (tmp, operands[lo]));
    emit_insn (gen_aarch64_float_truncate_hi_v4sf (operands[0],
						   tmp, operands[hi]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V4SFmode,
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand1),
	gen_rtx_FLOAT_TRUNCATE (V2SFmode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:1997 */
rtx
gen_vec_pack_trunc_df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2006 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx tmp = gen_reg_rtx (V2SFmode);
    int lo = BYTES_BIG_ENDIAN ? 2 : 1;
    int hi = BYTES_BIG_ENDIAN ? 1 : 2;

    emit_insn (gen_move_lo_quad_v2df (tmp, operands[lo]));
    emit_insn (gen_move_hi_quad_v2df (tmp, operands[hi]));
    emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_VEC_CONCAT (V2SFmode,
	gen_rtx_FLOAT_TRUNCATE (SFmode,
	operand1),
	gen_rtx_FLOAT_TRUNCATE (SFmode,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2056 */
rtx
gen_reduc_plus_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8QImode, 0));
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_plus_internalv8qi (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	78));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2056 */
rtx
gen_reduc_plus_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V16QImode, 0));
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_plus_internalv16qi (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	78));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2056 */
rtx
gen_reduc_plus_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HImode, 0));
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_plus_internalv4hi (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	78));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2056 */
rtx
gen_reduc_plus_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HImode, 0));
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_plus_internalv8hi (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	78));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2056 */
rtx
gen_reduc_plus_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SImode, 0));
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_plus_internalv2si (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	78));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2056 */
rtx
gen_reduc_plus_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SImode, 0));
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_plus_internalv4si (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	78));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2056 */
rtx
gen_reduc_plus_scal_v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2061 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2DImode, 0));
    rtx scratch = gen_reg_rtx (V2DImode);
    emit_insn (gen_aarch64_reduc_plus_internalv2di (scratch, operands[1]));
    emit_insn (gen_aarch64_get_lanev2di (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		operand1),
	78));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2107 */
rtx
gen_reduc_plus_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2112 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0));
  rtx scratch = gen_reg_rtx (V4SFmode);
  emit_insn (gen_aarch64_faddpv4sf (scratch, operands[1], operands[1]));
  emit_insn (gen_aarch64_faddpv4sf (scratch, scratch, scratch));
  emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	77)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_nan_scal_v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HFmode, 0));
    rtx scratch = gen_reg_rtx (V4HFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv4hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	73));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_nan_scal_v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HFmode, 0));
    rtx scratch = gen_reg_rtx (V4HFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv4hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	76));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_scal_v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HFmode, 0));
    rtx scratch = gen_reg_rtx (V4HFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv4hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	72));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_scal_v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HFmode, 0));
    rtx scratch = gen_reg_rtx (V4HFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv4hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		operand1),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_nan_scal_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HFmode, 0));
    rtx scratch = gen_reg_rtx (V8HFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv8hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	73));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_nan_scal_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HFmode, 0));
    rtx scratch = gen_reg_rtx (V8HFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv8hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	76));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_scal_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HFmode, 0));
    rtx scratch = gen_reg_rtx (V8HFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv8hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	72));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_scal_v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HFmode, 0));
    rtx scratch = gen_reg_rtx (V8HFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv8hf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		operand1),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_nan_scal_v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SFmode, 0));
    rtx scratch = gen_reg_rtx (V2SFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv2sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	73));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_nan_scal_v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SFmode, 0));
    rtx scratch = gen_reg_rtx (V2SFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv2sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	76));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_scal_v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SFmode, 0));
    rtx scratch = gen_reg_rtx (V2SFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv2sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	72));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_scal_v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SFmode, 0));
    rtx scratch = gen_reg_rtx (V2SFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv2sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		operand1),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_nan_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0));
    rtx scratch = gen_reg_rtx (V4SFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv4sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	73));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_nan_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0));
    rtx scratch = gen_reg_rtx (V4SFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv4sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	76));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0));
    rtx scratch = gen_reg_rtx (V4SFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv4sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	72));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_scal_v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SFmode, 0));
    rtx scratch = gen_reg_rtx (V4SFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv4sf (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4sf (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		operand1),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_nan_scal_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2DFmode, 0));
    rtx scratch = gen_reg_rtx (V2DFmode);
    emit_insn (gen_aarch64_reduc_smax_nan_internalv2df (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2df (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	73));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_nan_scal_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2DFmode, 0));
    rtx scratch = gen_reg_rtx (V2DFmode);
    emit_insn (gen_aarch64_reduc_smin_nan_internalv2df (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2df (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	76));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smax_scal_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2DFmode, 0));
    rtx scratch = gen_reg_rtx (V2DFmode);
    emit_insn (gen_aarch64_reduc_smax_internalv2df (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2df (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	72));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2149 */
rtx
gen_reduc_smin_scal_v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2154 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2DFmode, 0));
    rtx scratch = gen_reg_rtx (V2DFmode);
    emit_insn (gen_aarch64_reduc_smin_internalv2df (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2df (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		operand1),
	75));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umax_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8QImode, 0));
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_umax_internalv8qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	81));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umin_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8QImode, 0));
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_umin_internalv8qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	82));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smax_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8QImode, 0));
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_smax_internalv8qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	79));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smin_scal_v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8QImode, 0));
    rtx scratch = gen_reg_rtx (V8QImode);
    emit_insn (gen_aarch64_reduc_smin_internalv8qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		operand1),
	80));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umax_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V16QImode, 0));
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_umax_internalv16qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	81));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umin_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V16QImode, 0));
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_umin_internalv16qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	82));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smax_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V16QImode, 0));
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_smax_internalv16qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	79));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smin_scal_v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V16QImode, 0));
    rtx scratch = gen_reg_rtx (V16QImode);
    emit_insn (gen_aarch64_reduc_smin_internalv16qi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev16qi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		operand1),
	80));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umax_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HImode, 0));
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_umax_internalv4hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	81));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umin_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HImode, 0));
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_umin_internalv4hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	82));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smax_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HImode, 0));
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_smax_internalv4hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	79));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smin_scal_v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4HImode, 0));
    rtx scratch = gen_reg_rtx (V4HImode);
    emit_insn (gen_aarch64_reduc_smin_internalv4hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		operand1),
	80));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umax_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HImode, 0));
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_umax_internalv8hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	81));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umin_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HImode, 0));
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_umin_internalv8hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	82));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smax_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HImode, 0));
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_smax_internalv8hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	79));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smin_scal_v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V8HImode, 0));
    rtx scratch = gen_reg_rtx (V8HImode);
    emit_insn (gen_aarch64_reduc_smin_internalv8hi (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev8hi (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		operand1),
	80));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umax_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SImode, 0));
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_umax_internalv2si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	81));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umin_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SImode, 0));
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_umin_internalv2si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	82));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smax_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SImode, 0));
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_smax_internalv2si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	79));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smin_scal_v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V2SImode, 0));
    rtx scratch = gen_reg_rtx (V2SImode);
    emit_insn (gen_aarch64_reduc_smin_internalv2si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev2si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		operand1),
	80));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umax_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SImode, 0));
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_umax_internalv4si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	81));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_umin_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SImode, 0));
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_umin_internalv4si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	82));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smax_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SImode, 0));
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_smax_internalv4si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	79));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2165 */
rtx
gen_reduc_smin_scal_v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2170 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx elt = GEN_INT (ENDIAN_LANE_N (V4SImode, 0));
    rtx scratch = gen_reg_rtx (V4SImode);
    emit_insn (gen_aarch64_reduc_smin_internalv4si (scratch,
							      operands[1]));
    emit_insn (gen_aarch64_get_lanev4si (operands[0], scratch, elt));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		operand1),
	80));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V8QImode))
    {
      operands[2] = gen_lowpart (V8QImode, operands[2]);
      operands[3] = gen_lowpart (V8QImode, operands[3]);
      tmp = gen_reg_rtx (V8QImode);
    }
  operands[1] = gen_lowpart (V8QImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv8qi_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V8QImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V16QImode))
    {
      operands[2] = gen_lowpart (V16QImode, operands[2]);
      operands[3] = gen_lowpart (V16QImode, operands[3]);
      tmp = gen_reg_rtx (V16QImode);
    }
  operands[1] = gen_lowpart (V16QImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv16qi_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V16QImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V4HImode))
    {
      operands[2] = gen_lowpart (V4HImode, operands[2]);
      operands[3] = gen_lowpart (V4HImode, operands[3]);
      tmp = gen_reg_rtx (V4HImode);
    }
  operands[1] = gen_lowpart (V4HImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv4hi_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V4HImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V8HImode))
    {
      operands[2] = gen_lowpart (V8HImode, operands[2]);
      operands[3] = gen_lowpart (V8HImode, operands[3]);
      tmp = gen_reg_rtx (V8HImode);
    }
  operands[1] = gen_lowpart (V8HImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv8hi_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V8HImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V2SImode))
    {
      operands[2] = gen_lowpart (V2SImode, operands[2]);
      operands[3] = gen_lowpart (V2SImode, operands[3]);
      tmp = gen_reg_rtx (V2SImode);
    }
  operands[1] = gen_lowpart (V2SImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv2si_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V2SImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V4SImode))
    {
      operands[2] = gen_lowpart (V4SImode, operands[2]);
      operands[3] = gen_lowpart (V4SImode, operands[3]);
      tmp = gen_reg_rtx (V4SImode);
    }
  operands[1] = gen_lowpart (V4SImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv4si_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V4SImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V2DImode))
    {
      operands[2] = gen_lowpart (V2DImode, operands[2]);
      operands[3] = gen_lowpart (V2DImode, operands[3]);
      tmp = gen_reg_rtx (V2DImode);
    }
  operands[1] = gen_lowpart (V2DImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv2di_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V2DImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V4HFmode))
    {
      operands[2] = gen_lowpart (V4HImode, operands[2]);
      operands[3] = gen_lowpart (V4HImode, operands[3]);
      tmp = gen_reg_rtx (V4HImode);
    }
  operands[1] = gen_lowpart (V4HImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv4hi_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V4HFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V8HFmode))
    {
      operands[2] = gen_lowpart (V8HImode, operands[2]);
      operands[3] = gen_lowpart (V8HImode, operands[3]);
      tmp = gen_reg_rtx (V8HImode);
    }
  operands[1] = gen_lowpart (V8HImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv8hi_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V8HFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V2SFmode))
    {
      operands[2] = gen_lowpart (V2SImode, operands[2]);
      operands[3] = gen_lowpart (V2SImode, operands[3]);
      tmp = gen_reg_rtx (V2SImode);
    }
  operands[1] = gen_lowpart (V2SImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv2si_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V2SFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V4SFmode))
    {
      operands[2] = gen_lowpart (V4SImode, operands[2]);
      operands[3] = gen_lowpart (V4SImode, operands[3]);
      tmp = gen_reg_rtx (V4SImode);
    }
  operands[1] = gen_lowpart (V4SImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv4si_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V4SFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bslv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (V2DFmode))
    {
      operands[2] = gen_lowpart (V2DImode, operands[2]);
      operands[3] = gen_lowpart (V2DImode, operands[3]);
      tmp = gen_reg_rtx (V2DImode);
    }
  operands[1] = gen_lowpart (V2DImode, operands[1]);
  emit_insn (gen_aarch64_simd_bslv2di_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (V2DFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bsldi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (DImode))
    {
      operands[2] = gen_lowpart (DImode, operands[2]);
      operands[3] = gen_lowpart (DImode, operands[3]);
      tmp = gen_reg_rtx (DImode);
    }
  operands[1] = gen_lowpart (DImode, operands[1]);
  emit_insn (gen_aarch64_simd_bsldi_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (DImode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2268 */
rtx
gen_aarch64_simd_bsldf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  /* We can't alias operands together if they have different modes.  */
  rtx tmp = operands[0];
  if (FLOAT_MODE_P (DFmode))
    {
      operands[2] = gen_lowpart (DImode, operands[2]);
      operands[3] = gen_lowpart (DImode, operands[3]);
      tmp = gen_reg_rtx (DImode);
    }
  operands[1] = gen_lowpart (DImode, operands[1]);
  emit_insn (gen_aarch64_simd_bsldi_internal (tmp,
							  operands[1],
							  operands[2],
							  operands[3]));
  if (tmp != operands[0])
    emit_move_insn (operands[0], gen_lowpart (DFmode, tmp));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2294 */
rtx
gen_aarch64_vcond_internalv8qiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2303 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V8QImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
     and desirable for other comparisons if it results in FOO ? -1 : 0
     (this allows direct use of the comparison result without a bsl).  */
  if (code == NE
      || (code != EQ
	  && op1 == CONST0_RTX (V8QImode)
	  && op2 == CONSTM1_RTX (V8QImode)))
    {
      op1 = operands[2];
      op2 = operands[1];
      switch (code)
        {
        case LE: code = GT; break;
        case LT: code = GE; break;
        case GE: code = LT; break;
        case GT: code = LE; break;
        /* No case EQ.  */
        case NE: code = EQ; break;
        case LTU: code = GEU; break;
        case LEU: code = GTU; break;
        case GTU: code = LEU; break;
        case GEU: code = LTU; break;
        default: gcc_unreachable ();
        }
    }

  /* Make sure we can handle the last operand.  */
  switch (code)
    {
    case NE:
      /* Normalized to EQ above.  */
      gcc_unreachable ();

    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      /* These instructions have a form taking an immediate zero.  */
      if (operands[5] == CONST0_RTX (V8QImode))
        break;
      /* Fall through, as may need to load into register.  */
    default:
      if (!REG_P (operands[5]))
        operands[5] = force_reg (V8QImode, operands[5]);
      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv8qi (mask, operands[4], operands[5]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev8qi (mask, operands[4], operands[5]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev8qi (mask, operands[4], operands[5]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv8qi (mask, operands[4], operands[5]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv8qi (mask, operands[5], operands[4]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv8qi (mask, operands[4], operands[5]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv8qi (mask, operands[5], operands[4]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv8qi (mask, operands[4], operands[5]));
      break;

    /* NE has been normalized to EQ above.  */
    case EQ:
      emit_insn (gen_aarch64_cmeqv8qi (mask, operands[4], operands[5]));
      break;

    default:
      gcc_unreachable ();
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V8QImode)
	&& op2 == CONST0_RTX (V8QImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V8QImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V8QImode, op2);
	emit_insn (gen_aarch64_simd_bslv8qi (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2294 */
rtx
gen_aarch64_vcond_internalv16qiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2303 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V16QImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
     and desirable for other comparisons if it results in FOO ? -1 : 0
     (this allows direct use of the comparison result without a bsl).  */
  if (code == NE
      || (code != EQ
	  && op1 == CONST0_RTX (V16QImode)
	  && op2 == CONSTM1_RTX (V16QImode)))
    {
      op1 = operands[2];
      op2 = operands[1];
      switch (code)
        {
        case LE: code = GT; break;
        case LT: code = GE; break;
        case GE: code = LT; break;
        case GT: code = LE; break;
        /* No case EQ.  */
        case NE: code = EQ; break;
        case LTU: code = GEU; break;
        case LEU: code = GTU; break;
        case GTU: code = LEU; break;
        case GEU: code = LTU; break;
        default: gcc_unreachable ();
        }
    }

  /* Make sure we can handle the last operand.  */
  switch (code)
    {
    case NE:
      /* Normalized to EQ above.  */
      gcc_unreachable ();

    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      /* These instructions have a form taking an immediate zero.  */
      if (operands[5] == CONST0_RTX (V16QImode))
        break;
      /* Fall through, as may need to load into register.  */
    default:
      if (!REG_P (operands[5]))
        operands[5] = force_reg (V16QImode, operands[5]);
      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv16qi (mask, operands[4], operands[5]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev16qi (mask, operands[4], operands[5]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev16qi (mask, operands[4], operands[5]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv16qi (mask, operands[4], operands[5]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv16qi (mask, operands[5], operands[4]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv16qi (mask, operands[4], operands[5]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv16qi (mask, operands[5], operands[4]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv16qi (mask, operands[4], operands[5]));
      break;

    /* NE has been normalized to EQ above.  */
    case EQ:
      emit_insn (gen_aarch64_cmeqv16qi (mask, operands[4], operands[5]));
      break;

    default:
      gcc_unreachable ();
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V16QImode)
	&& op2 == CONST0_RTX (V16QImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V16QImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V16QImode, op2);
	emit_insn (gen_aarch64_simd_bslv16qi (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V16QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2294 */
rtx
gen_aarch64_vcond_internalv4hiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2303 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V4HImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
     and desirable for other comparisons if it results in FOO ? -1 : 0
     (this allows direct use of the comparison result without a bsl).  */
  if (code == NE
      || (code != EQ
	  && op1 == CONST0_RTX (V4HImode)
	  && op2 == CONSTM1_RTX (V4HImode)))
    {
      op1 = operands[2];
      op2 = operands[1];
      switch (code)
        {
        case LE: code = GT; break;
        case LT: code = GE; break;
        case GE: code = LT; break;
        case GT: code = LE; break;
        /* No case EQ.  */
        case NE: code = EQ; break;
        case LTU: code = GEU; break;
        case LEU: code = GTU; break;
        case GTU: code = LEU; break;
        case GEU: code = LTU; break;
        default: gcc_unreachable ();
        }
    }

  /* Make sure we can handle the last operand.  */
  switch (code)
    {
    case NE:
      /* Normalized to EQ above.  */
      gcc_unreachable ();

    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      /* These instructions have a form taking an immediate zero.  */
      if (operands[5] == CONST0_RTX (V4HImode))
        break;
      /* Fall through, as may need to load into register.  */
    default:
      if (!REG_P (operands[5]))
        operands[5] = force_reg (V4HImode, operands[5]);
      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv4hi (mask, operands[4], operands[5]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev4hi (mask, operands[4], operands[5]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev4hi (mask, operands[4], operands[5]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv4hi (mask, operands[4], operands[5]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv4hi (mask, operands[5], operands[4]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv4hi (mask, operands[4], operands[5]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv4hi (mask, operands[5], operands[4]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv4hi (mask, operands[4], operands[5]));
      break;

    /* NE has been normalized to EQ above.  */
    case EQ:
      emit_insn (gen_aarch64_cmeqv4hi (mask, operands[4], operands[5]));
      break;

    default:
      gcc_unreachable ();
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V4HImode)
	&& op2 == CONST0_RTX (V4HImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V4HImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V4HImode, op2);
	emit_insn (gen_aarch64_simd_bslv4hi (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2294 */
rtx
gen_aarch64_vcond_internalv8hiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2303 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V8HImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
     and desirable for other comparisons if it results in FOO ? -1 : 0
     (this allows direct use of the comparison result without a bsl).  */
  if (code == NE
      || (code != EQ
	  && op1 == CONST0_RTX (V8HImode)
	  && op2 == CONSTM1_RTX (V8HImode)))
    {
      op1 = operands[2];
      op2 = operands[1];
      switch (code)
        {
        case LE: code = GT; break;
        case LT: code = GE; break;
        case GE: code = LT; break;
        case GT: code = LE; break;
        /* No case EQ.  */
        case NE: code = EQ; break;
        case LTU: code = GEU; break;
        case LEU: code = GTU; break;
        case GTU: code = LEU; break;
        case GEU: code = LTU; break;
        default: gcc_unreachable ();
        }
    }

  /* Make sure we can handle the last operand.  */
  switch (code)
    {
    case NE:
      /* Normalized to EQ above.  */
      gcc_unreachable ();

    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      /* These instructions have a form taking an immediate zero.  */
      if (operands[5] == CONST0_RTX (V8HImode))
        break;
      /* Fall through, as may need to load into register.  */
    default:
      if (!REG_P (operands[5]))
        operands[5] = force_reg (V8HImode, operands[5]);
      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv8hi (mask, operands[4], operands[5]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev8hi (mask, operands[4], operands[5]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev8hi (mask, operands[4], operands[5]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv8hi (mask, operands[4], operands[5]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv8hi (mask, operands[5], operands[4]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv8hi (mask, operands[4], operands[5]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv8hi (mask, operands[5], operands[4]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv8hi (mask, operands[4], operands[5]));
      break;

    /* NE has been normalized to EQ above.  */
    case EQ:
      emit_insn (gen_aarch64_cmeqv8hi (mask, operands[4], operands[5]));
      break;

    default:
      gcc_unreachable ();
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V8HImode)
	&& op2 == CONST0_RTX (V8HImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V8HImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V8HImode, op2);
	emit_insn (gen_aarch64_simd_bslv8hi (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2294 */
rtx
gen_aarch64_vcond_internalv2siv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2303 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
     and desirable for other comparisons if it results in FOO ? -1 : 0
     (this allows direct use of the comparison result without a bsl).  */
  if (code == NE
      || (code != EQ
	  && op1 == CONST0_RTX (V2SImode)
	  && op2 == CONSTM1_RTX (V2SImode)))
    {
      op1 = operands[2];
      op2 = operands[1];
      switch (code)
        {
        case LE: code = GT; break;
        case LT: code = GE; break;
        case GE: code = LT; break;
        case GT: code = LE; break;
        /* No case EQ.  */
        case NE: code = EQ; break;
        case LTU: code = GEU; break;
        case LEU: code = GTU; break;
        case GTU: code = LEU; break;
        case GEU: code = LTU; break;
        default: gcc_unreachable ();
        }
    }

  /* Make sure we can handle the last operand.  */
  switch (code)
    {
    case NE:
      /* Normalized to EQ above.  */
      gcc_unreachable ();

    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      /* These instructions have a form taking an immediate zero.  */
      if (operands[5] == CONST0_RTX (V2SImode))
        break;
      /* Fall through, as may need to load into register.  */
    default:
      if (!REG_P (operands[5]))
        operands[5] = force_reg (V2SImode, operands[5]);
      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv2si (mask, operands[4], operands[5]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev2si (mask, operands[4], operands[5]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev2si (mask, operands[4], operands[5]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv2si (mask, operands[4], operands[5]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv2si (mask, operands[5], operands[4]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv2si (mask, operands[4], operands[5]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv2si (mask, operands[5], operands[4]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv2si (mask, operands[4], operands[5]));
      break;

    /* NE has been normalized to EQ above.  */
    case EQ:
      emit_insn (gen_aarch64_cmeqv2si (mask, operands[4], operands[5]));
      break;

    default:
      gcc_unreachable ();
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2SImode)
	&& op2 == CONST0_RTX (V2SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2SImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2SImode, op2);
	emit_insn (gen_aarch64_simd_bslv2si (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2294 */
rtx
gen_aarch64_vcond_internalv4siv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2303 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V4SImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
     and desirable for other comparisons if it results in FOO ? -1 : 0
     (this allows direct use of the comparison result without a bsl).  */
  if (code == NE
      || (code != EQ
	  && op1 == CONST0_RTX (V4SImode)
	  && op2 == CONSTM1_RTX (V4SImode)))
    {
      op1 = operands[2];
      op2 = operands[1];
      switch (code)
        {
        case LE: code = GT; break;
        case LT: code = GE; break;
        case GE: code = LT; break;
        case GT: code = LE; break;
        /* No case EQ.  */
        case NE: code = EQ; break;
        case LTU: code = GEU; break;
        case LEU: code = GTU; break;
        case GTU: code = LEU; break;
        case GEU: code = LTU; break;
        default: gcc_unreachable ();
        }
    }

  /* Make sure we can handle the last operand.  */
  switch (code)
    {
    case NE:
      /* Normalized to EQ above.  */
      gcc_unreachable ();

    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      /* These instructions have a form taking an immediate zero.  */
      if (operands[5] == CONST0_RTX (V4SImode))
        break;
      /* Fall through, as may need to load into register.  */
    default:
      if (!REG_P (operands[5]))
        operands[5] = force_reg (V4SImode, operands[5]);
      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv4si (mask, operands[4], operands[5]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev4si (mask, operands[4], operands[5]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev4si (mask, operands[4], operands[5]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv4si (mask, operands[4], operands[5]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv4si (mask, operands[5], operands[4]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv4si (mask, operands[4], operands[5]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv4si (mask, operands[5], operands[4]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv4si (mask, operands[4], operands[5]));
      break;

    /* NE has been normalized to EQ above.  */
    case EQ:
      emit_insn (gen_aarch64_cmeqv4si (mask, operands[4], operands[5]));
      break;

    default:
      gcc_unreachable ();
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V4SImode)
	&& op2 == CONST0_RTX (V4SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V4SImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V4SImode, op2);
	emit_insn (gen_aarch64_simd_bslv4si (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2294 */
rtx
gen_aarch64_vcond_internalv2div2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2303 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
     and desirable for other comparisons if it results in FOO ? -1 : 0
     (this allows direct use of the comparison result without a bsl).  */
  if (code == NE
      || (code != EQ
	  && op1 == CONST0_RTX (V2DImode)
	  && op2 == CONSTM1_RTX (V2DImode)))
    {
      op1 = operands[2];
      op2 = operands[1];
      switch (code)
        {
        case LE: code = GT; break;
        case LT: code = GE; break;
        case GE: code = LT; break;
        case GT: code = LE; break;
        /* No case EQ.  */
        case NE: code = EQ; break;
        case LTU: code = GEU; break;
        case LEU: code = GTU; break;
        case GTU: code = LEU; break;
        case GEU: code = LTU; break;
        default: gcc_unreachable ();
        }
    }

  /* Make sure we can handle the last operand.  */
  switch (code)
    {
    case NE:
      /* Normalized to EQ above.  */
      gcc_unreachable ();

    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      /* These instructions have a form taking an immediate zero.  */
      if (operands[5] == CONST0_RTX (V2DImode))
        break;
      /* Fall through, as may need to load into register.  */
    default:
      if (!REG_P (operands[5]))
        operands[5] = force_reg (V2DImode, operands[5]);
      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltv2di (mask, operands[4], operands[5]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgev2di (mask, operands[4], operands[5]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmlev2di (mask, operands[4], operands[5]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtv2di (mask, operands[4], operands[5]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtuv2di (mask, operands[5], operands[4]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeuv2di (mask, operands[4], operands[5]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeuv2di (mask, operands[5], operands[4]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtuv2di (mask, operands[4], operands[5]));
      break;

    /* NE has been normalized to EQ above.  */
    case EQ:
      emit_insn (gen_aarch64_cmeqv2di (mask, operands[4], operands[5]));
      break;

    default:
      gcc_unreachable ();
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2DImode)
	&& op2 == CONST0_RTX (V2DImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2DImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2DImode, op2);
	emit_insn (gen_aarch64_simd_bslv2di (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2294 */
rtx
gen_aarch64_vcond_internaldidi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2303 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (DImode);
  enum rtx_code code = GET_CODE (operands[3]);

  /* Switching OP1 and OP2 is necessary for NE (to output a cmeq insn),
     and desirable for other comparisons if it results in FOO ? -1 : 0
     (this allows direct use of the comparison result without a bsl).  */
  if (code == NE
      || (code != EQ
	  && op1 == CONST0_RTX (DImode)
	  && op2 == CONSTM1_RTX (DImode)))
    {
      op1 = operands[2];
      op2 = operands[1];
      switch (code)
        {
        case LE: code = GT; break;
        case LT: code = GE; break;
        case GE: code = LT; break;
        case GT: code = LE; break;
        /* No case EQ.  */
        case NE: code = EQ; break;
        case LTU: code = GEU; break;
        case LEU: code = GTU; break;
        case GTU: code = LEU; break;
        case GEU: code = LTU; break;
        default: gcc_unreachable ();
        }
    }

  /* Make sure we can handle the last operand.  */
  switch (code)
    {
    case NE:
      /* Normalized to EQ above.  */
      gcc_unreachable ();

    case LE:
    case LT:
    case GE:
    case GT:
    case EQ:
      /* These instructions have a form taking an immediate zero.  */
      if (operands[5] == CONST0_RTX (DImode))
        break;
      /* Fall through, as may need to load into register.  */
    default:
      if (!REG_P (operands[5]))
        operands[5] = force_reg (DImode, operands[5]);
      break;
    }

  switch (code)
    {
    case LT:
      emit_insn (gen_aarch64_cmltdi (mask, operands[4], operands[5]));
      break;

    case GE:
      emit_insn (gen_aarch64_cmgedi (mask, operands[4], operands[5]));
      break;

    case LE:
      emit_insn (gen_aarch64_cmledi (mask, operands[4], operands[5]));
      break;

    case GT:
      emit_insn (gen_aarch64_cmgtdi (mask, operands[4], operands[5]));
      break;

    case LTU:
      emit_insn (gen_aarch64_cmgtudi (mask, operands[5], operands[4]));
      break;

    case GEU:
      emit_insn (gen_aarch64_cmgeudi (mask, operands[4], operands[5]));
      break;

    case LEU:
      emit_insn (gen_aarch64_cmgeudi (mask, operands[5], operands[4]));
      break;

    case GTU:
      emit_insn (gen_aarch64_cmgtudi (mask, operands[4], operands[5]));
      break;

    /* NE has been normalized to EQ above.  */
    case EQ:
      emit_insn (gen_aarch64_cmeqdi (mask, operands[4], operands[5]));
      break;

    default:
      gcc_unreachable ();
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (DImode)
	&& op2 == CONST0_RTX (DImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (DImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (DImode, op2);
	emit_insn (gen_aarch64_simd_bsldi (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2sfv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2SImode);
  rtx tmp = gen_reg_rtx (V2SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2sf;
      complimentary_comparison = gen_aarch64_cmgtv2sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2sf;
      complimentary_comparison = gen_aarch64_cmgev2sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2sf;
      complimentary_comparison = gen_aarch64_cmeqv2sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2SImode)
	&& op2 == CONST0_RTX (V2SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2SFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2SFmode, op2);
	emit_insn (gen_aarch64_simd_bslv2sf (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2siv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2SImode);
  rtx tmp = gen_reg_rtx (V2SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2sf;
      complimentary_comparison = gen_aarch64_cmgtv2sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2sf;
      complimentary_comparison = gen_aarch64_cmgev2sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2sf;
      complimentary_comparison = gen_aarch64_cmeqv2sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2SImode)
	&& op2 == CONST0_RTX (V2SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2SImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2SImode, op2);
	emit_insn (gen_aarch64_simd_bslv2si (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv4sfv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V4SImode);
  rtx tmp = gen_reg_rtx (V4SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2sf;
      complimentary_comparison = gen_aarch64_cmgtv2sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2sf;
      complimentary_comparison = gen_aarch64_cmgev2sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2sf;
      complimentary_comparison = gen_aarch64_cmeqv2sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V4SImode)
	&& op2 == CONST0_RTX (V4SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V4SFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V4SFmode, op2);
	emit_insn (gen_aarch64_simd_bslv4sf (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv4siv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V4SImode);
  rtx tmp = gen_reg_rtx (V4SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2sf;
      complimentary_comparison = gen_aarch64_cmgtv2sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2sf;
      complimentary_comparison = gen_aarch64_cmgev2sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2sf;
      complimentary_comparison = gen_aarch64_cmeqv2sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V4SImode)
	&& op2 == CONST0_RTX (V4SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V4SImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V4SImode, op2);
	emit_insn (gen_aarch64_simd_bslv4si (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2dfv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2DImode);
  rtx tmp = gen_reg_rtx (V2DImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2sf;
      complimentary_comparison = gen_aarch64_cmgtv2sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2sf;
      complimentary_comparison = gen_aarch64_cmgev2sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2sf;
      complimentary_comparison = gen_aarch64_cmeqv2sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2DImode)
	&& op2 == CONST0_RTX (V2DImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2DFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2DFmode, op2);
	emit_insn (gen_aarch64_simd_bslv2df (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2div2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2DImode);
  rtx tmp = gen_reg_rtx (V2DImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2sf;
      complimentary_comparison = gen_aarch64_cmgtv2sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2sf;
      complimentary_comparison = gen_aarch64_cmgev2sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2sf;
      complimentary_comparison = gen_aarch64_cmeqv2sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2DImode)
	&& op2 == CONST0_RTX (V2DImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2DImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2DImode, op2);
	emit_insn (gen_aarch64_simd_bslv2di (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2sfv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2SImode);
  rtx tmp = gen_reg_rtx (V2SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V4SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V4SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev4sf;
      complimentary_comparison = gen_aarch64_cmgtv4sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv4sf;
      complimentary_comparison = gen_aarch64_cmgev4sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv4sf;
      complimentary_comparison = gen_aarch64_cmeqv4sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv4sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev4sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv4sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev4sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2SImode)
	&& op2 == CONST0_RTX (V2SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2SFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2SFmode, op2);
	emit_insn (gen_aarch64_simd_bslv2sf (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2siv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2SImode);
  rtx tmp = gen_reg_rtx (V2SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V4SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V4SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev4sf;
      complimentary_comparison = gen_aarch64_cmgtv4sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv4sf;
      complimentary_comparison = gen_aarch64_cmgev4sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv4sf;
      complimentary_comparison = gen_aarch64_cmeqv4sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv4sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev4sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv4sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev4sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2SImode)
	&& op2 == CONST0_RTX (V2SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2SImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2SImode, op2);
	emit_insn (gen_aarch64_simd_bslv2si (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv4sfv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V4SImode);
  rtx tmp = gen_reg_rtx (V4SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V4SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V4SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev4sf;
      complimentary_comparison = gen_aarch64_cmgtv4sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv4sf;
      complimentary_comparison = gen_aarch64_cmgev4sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv4sf;
      complimentary_comparison = gen_aarch64_cmeqv4sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv4sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev4sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv4sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev4sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V4SImode)
	&& op2 == CONST0_RTX (V4SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V4SFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V4SFmode, op2);
	emit_insn (gen_aarch64_simd_bslv4sf (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv4siv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V4SImode);
  rtx tmp = gen_reg_rtx (V4SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V4SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V4SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev4sf;
      complimentary_comparison = gen_aarch64_cmgtv4sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv4sf;
      complimentary_comparison = gen_aarch64_cmgev4sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv4sf;
      complimentary_comparison = gen_aarch64_cmeqv4sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv4sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev4sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv4sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev4sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V4SImode)
	&& op2 == CONST0_RTX (V4SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V4SImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V4SImode, op2);
	emit_insn (gen_aarch64_simd_bslv4si (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2dfv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2DImode);
  rtx tmp = gen_reg_rtx (V2DImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V4SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V4SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev4sf;
      complimentary_comparison = gen_aarch64_cmgtv4sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv4sf;
      complimentary_comparison = gen_aarch64_cmgev4sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv4sf;
      complimentary_comparison = gen_aarch64_cmeqv4sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv4sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev4sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv4sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev4sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2DImode)
	&& op2 == CONST0_RTX (V2DImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2DFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2DFmode, op2);
	emit_insn (gen_aarch64_simd_bslv2df (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2div4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2DImode);
  rtx tmp = gen_reg_rtx (V2DImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V4SFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V4SFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev4sf;
      complimentary_comparison = gen_aarch64_cmgtv4sf;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv4sf;
      complimentary_comparison = gen_aarch64_cmgev4sf;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv4sf;
      complimentary_comparison = gen_aarch64_cmeqv4sf;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv4sf;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev4sf;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv4sf (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv4sf (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev4sf (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2DImode)
	&& op2 == CONST0_RTX (V2DImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2DImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2DImode, op2);
	emit_insn (gen_aarch64_simd_bslv2di (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2sfv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2SImode);
  rtx tmp = gen_reg_rtx (V2SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2DFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2DFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2df;
      complimentary_comparison = gen_aarch64_cmgtv2df;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2df;
      complimentary_comparison = gen_aarch64_cmgev2df;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2df;
      complimentary_comparison = gen_aarch64_cmeqv2df;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2df;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2df;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2df (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2df (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2SImode)
	&& op2 == CONST0_RTX (V2SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2SFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2SFmode, op2);
	emit_insn (gen_aarch64_simd_bslv2sf (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2siv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2SImode);
  rtx tmp = gen_reg_rtx (V2SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2DFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2DFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2df;
      complimentary_comparison = gen_aarch64_cmgtv2df;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2df;
      complimentary_comparison = gen_aarch64_cmgev2df;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2df;
      complimentary_comparison = gen_aarch64_cmeqv2df;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2df;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2df;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2df (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2df (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2SImode)
	&& op2 == CONST0_RTX (V2SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2SImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2SImode, op2);
	emit_insn (gen_aarch64_simd_bslv2si (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv4sfv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V4SImode);
  rtx tmp = gen_reg_rtx (V4SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2DFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2DFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2df;
      complimentary_comparison = gen_aarch64_cmgtv2df;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2df;
      complimentary_comparison = gen_aarch64_cmgev2df;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2df;
      complimentary_comparison = gen_aarch64_cmeqv2df;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2df;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2df;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2df (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2df (mask, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V4SImode)
	&& op2 == CONST0_RTX (V4SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V4SFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V4SFmode, op2);
	emit_insn (gen_aarch64_simd_bslv4sf (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv4siv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V4SImode);
  rtx tmp = gen_reg_rtx (V4SImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2DFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2DFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2df;
      complimentary_comparison = gen_aarch64_cmgtv2df;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2df;
      complimentary_comparison = gen_aarch64_cmgev2df;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2df;
      complimentary_comparison = gen_aarch64_cmeqv2df;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2df;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2df;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2df (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2df (mask, operands[5], operands[4]));
      emit_insn (gen_iorv4si3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V4SImode)
	&& op2 == CONST0_RTX (V4SImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V4SImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V4SImode, op2);
	emit_insn (gen_aarch64_simd_bslv4si (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2dfv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2DImode);
  rtx tmp = gen_reg_rtx (V2DImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2DFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2DFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2df;
      complimentary_comparison = gen_aarch64_cmgtv2df;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2df;
      complimentary_comparison = gen_aarch64_cmgev2df;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2df;
      complimentary_comparison = gen_aarch64_cmeqv2df;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2df;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2df;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2df (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2df (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2DImode)
	&& op2 == CONST0_RTX (V2DImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2DFmode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2DFmode, op2);
	emit_insn (gen_aarch64_simd_bslv2df (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2419 */
rtx
gen_aarch64_vcond_internalv2div2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2428 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int inverse = 0;
  int use_zero_form = 0;
  int swap_bsl_operands = 0;
  rtx op1 = operands[1];
  rtx op2 = operands[2];
  rtx mask = gen_reg_rtx (V2DImode);
  rtx tmp = gen_reg_rtx (V2DImode);

  rtx (*base_comparison) (rtx, rtx, rtx);
  rtx (*complimentary_comparison) (rtx, rtx, rtx);

  switch (GET_CODE (operands[3]))
    {
    case GE:
    case GT:
    case LE:
    case LT:
    case EQ:
      if (operands[5] == CONST0_RTX (V2DFmode))
	{
	  use_zero_form = 1;
	  break;
	}
      /* Fall through.  */
    default:
      if (!REG_P (operands[5]))
	operands[5] = force_reg (V2DFmode, operands[5]);
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case UNLT:
      inverse = 1;
      /* Fall through.  */
    case GE:
    case UNGE:
    case ORDERED:
    case UNORDERED:
      base_comparison = gen_aarch64_cmgev2df;
      complimentary_comparison = gen_aarch64_cmgtv2df;
      break;
    case LE:
    case UNLE:
      inverse = 1;
      /* Fall through.  */
    case GT:
    case UNGT:
      base_comparison = gen_aarch64_cmgtv2df;
      complimentary_comparison = gen_aarch64_cmgev2df;
      break;
    case EQ:
    case NE:
    case UNEQ:
      base_comparison = gen_aarch64_cmeqv2df;
      complimentary_comparison = gen_aarch64_cmeqv2df;
      break;
    default:
      gcc_unreachable ();
    }

  switch (GET_CODE (operands[3]))
    {
    case LT:
    case LE:
    case GT:
    case GE:
    case EQ:
      /* The easy case.  Here we emit one of FCMGE, FCMGT or FCMEQ.
	 As a LT b <=> b GE a && a LE b <=> b GT a.  Our transformations are:
	 a GE b -> a GE b
	 a GT b -> a GT b
	 a LE b -> b GE a
	 a LT b -> b GT a
	 a EQ b -> a EQ b
	 Note that there also exist direct comparison against 0 forms,
	 so catch those as a special case.  */
      if (use_zero_form)
	{
	  inverse = 0;
	  switch (GET_CODE (operands[3]))
	    {
	    case LT:
	      base_comparison = gen_aarch64_cmltv2df;
	      break;
	    case LE:
	      base_comparison = gen_aarch64_cmlev2df;
	      break;
	    default:
	      /* Do nothing, other zero form cases already have the correct
		 base_comparison.  */
	      break;
	    }
	}

      if (!inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));
      break;
    case UNLT:
    case UNLE:
    case UNGT:
    case UNGE:
    case NE:
      /* FCM returns false for lanes which are unordered, so if we use
	 the inverse of the comparison we actually want to emit, then
	 swap the operands to BSL, we will end up with the correct result.
	 Note that a NE NaN and NaN NE b are true for all a, b.

	 Our transformations are:
	 a GE b -> !(b GT a)
	 a GT b -> !(b GE a)
	 a LE b -> !(a GT b)
	 a LT b -> !(a GE b)
	 a NE b -> !(a EQ b)  */

      if (inverse)
	emit_insn (base_comparison (mask, operands[4], operands[5]));
      else
	emit_insn (complimentary_comparison (mask, operands[5], operands[4]));

      swap_bsl_operands = 1;
      break;
    case UNEQ:
      /* We check (a > b ||  b > a).  combining these comparisons give us
	 true iff !(a != b && a ORDERED b), swapping the operands to BSL
	 will then give us (a == b ||  a UNORDERED b) as intended.  */

      emit_insn (gen_aarch64_cmgtv2df (mask, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      swap_bsl_operands = 1;
      break;
    case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a).
	 Swapping the operands to BSL will give the UNORDERED case.  */
     swap_bsl_operands = 1;
     /* Fall through.  */
    case ORDERED:
      emit_insn (gen_aarch64_cmgtv2df (tmp, operands[4], operands[5]));
      emit_insn (gen_aarch64_cmgev2df (mask, operands[5], operands[4]));
      emit_insn (gen_iorv2di3 (mask, mask, tmp));
      break;
    default:
      gcc_unreachable ();
    }

  if (swap_bsl_operands)
    {
      op1 = operands[2];
      op2 = operands[1];
    }

    /* If we have (a = (b CMP c) ? -1 : 0);
       Then we can simply move the generated mask.  */

    if (op1 == CONSTM1_RTX (V2DImode)
	&& op2 == CONST0_RTX (V2DImode))
      emit_move_insn (operands[0], mask);
    else
      {
	if (!REG_P (op1))
	  op1 = force_reg (V2DImode, op1);
	if (!REG_P (op2))
	  op2 = force_reg (V2DImode, op2);
	emit_insn (gen_aarch64_simd_bslv2di (operands[0], mask,
					       op1, op2));
      }

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv8qiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv8qiv8qi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv16qiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv16qiv16qi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V16QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv4hiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv4hiv4hi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv8hiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv8hiv8hi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv2siv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv2siv2si (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv4siv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv4siv4si (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv2div2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv2sfv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv2sfv2sf (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv4sfv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv4sfv4sf (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vcondv2dfv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv2dfv2df (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DFmode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2602 */
rtx
gen_vconddidi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2611 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internaldidi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2618 */
rtx
gen_vcondv2siv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv2siv2sf (
						operands[0], operands[1],
						operands[2], operands[3],
						operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2618 */
rtx
gen_vcondv4siv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv4siv4sf (
						operands[0], operands[1],
						operands[2], operands[3],
						operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2618 */
rtx
gen_vcondv2div2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv2div2df (
						operands[0], operands[1],
						operands[2], operands[3],
						operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2635 */
rtx
gen_vconduv8qiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2644 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv8qiv8qi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2635 */
rtx
gen_vconduv16qiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2644 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv16qiv16qi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V16QImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2635 */
rtx
gen_vconduv4hiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2644 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv4hiv4hi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2635 */
rtx
gen_vconduv8hiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2644 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv8hiv8hi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V8HImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2635 */
rtx
gen_vconduv2siv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2644 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv2siv2si (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2635 */
rtx
gen_vconduv4siv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2644 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv4siv4si (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V4SImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2635 */
rtx
gen_vconduv2div2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2644 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (V2DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2635 */
rtx
gen_vcondudidi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[6];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2644 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_vcond_internaldidi (operands[0], operands[1],
					       operands[2], operands[3],
					       operands[4], operands[5]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_IF_THEN_ELSE (DImode,
	gen_rtx_fmt_ee (GET_CODE (operand3), VOIDmode,
		operand4,
		operand5),
	operand1,
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2741 */
rtx
gen_aarch64_combinev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2746 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1, op2;
  if (BYTES_BIG_ENDIAN)
    {
      op1 = operands[2];
      op2 = operands[1];
    }
  else
    {
      op1 = operands[1];
      op2 = operands[2];
    }
  emit_insn (gen_aarch64_combine_internalv8qi (operands[0], op1, op2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2741 */
rtx
gen_aarch64_combinev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2746 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1, op2;
  if (BYTES_BIG_ENDIAN)
    {
      op1 = operands[2];
      op2 = operands[1];
    }
  else
    {
      op1 = operands[1];
      op2 = operands[2];
    }
  emit_insn (gen_aarch64_combine_internalv4hi (operands[0], op1, op2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2741 */
rtx
gen_aarch64_combinev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2746 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1, op2;
  if (BYTES_BIG_ENDIAN)
    {
      op1 = operands[2];
      op2 = operands[1];
    }
  else
    {
      op1 = operands[1];
      op2 = operands[2];
    }
  emit_insn (gen_aarch64_combine_internalv4hf (operands[0], op1, op2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2741 */
rtx
gen_aarch64_combinev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2746 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1, op2;
  if (BYTES_BIG_ENDIAN)
    {
      op1 = operands[2];
      op2 = operands[1];
    }
  else
    {
      op1 = operands[1];
      op2 = operands[2];
    }
  emit_insn (gen_aarch64_combine_internalv2si (operands[0], op1, op2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2741 */
rtx
gen_aarch64_combinev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2746 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1, op2;
  if (BYTES_BIG_ENDIAN)
    {
      op1 = operands[2];
      op2 = operands[1];
    }
  else
    {
      op1 = operands[1];
      op2 = operands[2];
    }
  emit_insn (gen_aarch64_combine_internalv2sf (operands[0], op1, op2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2741 */
rtx
gen_aarch64_combinedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2746 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1, op2;
  if (BYTES_BIG_ENDIAN)
    {
      op1 = operands[2];
      op2 = operands[1];
    }
  else
    {
      op1 = operands[1];
      op2 = operands[2];
    }
  emit_insn (gen_aarch64_combine_internaldi (operands[0], op1, op2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2741 */
rtx
gen_aarch64_combinedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2746 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx op1, op2;
  if (BYTES_BIG_ENDIAN)
    {
      op1 = operands[2];
      op2 = operands[1];
    }
  else
    {
      op1 = operands[1];
      op2 = operands[2];
    }
  emit_insn (gen_aarch64_combine_internaldf (operands[0], op1, op2));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
extern rtx_insn *gen_split_43 (rtx_insn *, rtx *);
rtx_insn *
gen_split_43 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_43\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2771 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
  else
    aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
extern rtx_insn *gen_split_44 (rtx_insn *, rtx *);
rtx_insn *
gen_split_44 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_44\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2771 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
  else
    aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
extern rtx_insn *gen_split_45 (rtx_insn *, rtx *);
rtx_insn *
gen_split_45 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_45\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2771 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
  else
    aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
extern rtx_insn *gen_split_46 (rtx_insn *, rtx *);
rtx_insn *
gen_split_46 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_46\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2771 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
  else
    aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
extern rtx_insn *gen_split_47 (rtx_insn *, rtx *);
rtx_insn *
gen_split_47 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_47\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2771 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
  else
    aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
extern rtx_insn *gen_split_48 (rtx_insn *, rtx *);
rtx_insn *
gen_split_48 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_48\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2771 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
  else
    aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2763 */
extern rtx_insn *gen_split_49 (rtx_insn *, rtx *);
rtx_insn *
gen_split_49 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_49\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2771 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    aarch64_split_simd_combine (operands[0], operands[2], operands[1]);
  else
    aarch64_split_simd_combine (operands[0], operands[1], operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2781 */
rtx
gen_aarch64_simd_combinev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2786 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v16qi (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v16qi (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2781 */
rtx
gen_aarch64_simd_combinev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2786 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v8hi (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v8hi (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2781 */
rtx
gen_aarch64_simd_combinev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2786 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v8hf (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v8hf (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2781 */
rtx
gen_aarch64_simd_combinev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2786 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v4si (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v4si (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2781 */
rtx
gen_aarch64_simd_combinev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2786 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v4sf (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v4sf (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2781 */
rtx
gen_aarch64_simd_combinedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2786 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v2di (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v2di (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2781 */
rtx
gen_aarch64_simd_combinedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2786 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn (gen_move_lo_quad_v2df (operands[0], operands[1]));
    emit_insn (gen_move_hi_quad_v2df (operands[0], operands[2]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2823 */
rtx
gen_aarch64_saddl2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2828 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
  emit_insn (gen_aarch64_saddlv16qi_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2823 */
rtx
gen_aarch64_saddl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2828 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_saddlv8hi_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2823 */
rtx
gen_aarch64_saddl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2828 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_saddlv4si_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2835 */
rtx
gen_aarch64_uaddl2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2840 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
  emit_insn (gen_aarch64_uaddlv16qi_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2835 */
rtx
gen_aarch64_uaddl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2840 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_uaddlv8hi_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2835 */
rtx
gen_aarch64_uaddl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2840 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_uaddlv4si_hi_internal (operands[0], operands[1],
                                                  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2847 */
rtx
gen_aarch64_ssubl2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2852 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
  emit_insn (gen_aarch64_ssublv16qi_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2847 */
rtx
gen_aarch64_ssubl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2852 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_ssublv8hi_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2847 */
rtx
gen_aarch64_ssubl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2852 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_ssublv4si_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2859 */
rtx
gen_aarch64_usubl2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2864 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
  emit_insn (gen_aarch64_usublv16qi_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2859 */
rtx
gen_aarch64_usubl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2864 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_usublv8hi_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2859 */
rtx
gen_aarch64_usubl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2864 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_usublv4si_hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2884 */
rtx
gen_widen_ssumv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2890 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_saddwv16qi_internal (temp, operands[2],
						operands[1], p));
    emit_insn (gen_aarch64_saddw2v16qi (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2884 */
rtx
gen_widen_ssumv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2890 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_saddwv8hi_internal (temp, operands[2],
						operands[1], p));
    emit_insn (gen_aarch64_saddw2v8hi (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2884 */
rtx
gen_widen_ssumv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2890 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_saddwv4si_internal (temp, operands[2],
						operands[1], p));
    emit_insn (gen_aarch64_saddw2v4si (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2901 */
rtx
gen_widen_ssumv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2907 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_saddwv8qi (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_SIGN_EXTEND (V8HImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2901 */
rtx
gen_widen_ssumv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2907 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_saddwv4hi (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_SIGN_EXTEND (V4SImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2901 */
rtx
gen_widen_ssumv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2907 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_saddwv2si (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_SIGN_EXTEND (V2DImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2912 */
rtx
gen_widen_usumv16qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2918 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_uaddwv16qi_internal (temp, operands[2],
						 operands[1], p));
    emit_insn (gen_aarch64_uaddw2v16qi (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2912 */
rtx
gen_widen_usumv8hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2918 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_uaddwv8hi_internal (temp, operands[2],
						 operands[1], p));
    emit_insn (gen_aarch64_uaddw2v8hi (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2912 */
rtx
gen_widen_usumv4si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2918 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, false);
    rtx temp = gen_reg_rtx (GET_MODE (operands[0]));

    emit_insn (gen_aarch64_uaddwv4si_internal (temp, operands[2],
						 operands[1], p));
    emit_insn (gen_aarch64_uaddw2v4si (operands[0], temp, operands[1]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2929 */
rtx
gen_widen_usumv8qi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2935 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_uaddwv8qi (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V8HImode,
	gen_rtx_ZERO_EXTEND (V8HImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2929 */
rtx
gen_widen_usumv4hi3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2935 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_uaddwv4hi (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V4SImode,
	gen_rtx_ZERO_EXTEND (V4SImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2929 */
rtx
gen_widen_usumv2si3 (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2935 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  emit_insn (gen_aarch64_uaddwv2si (operands[0], operands[2], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_PLUS (V2DImode,
	gen_rtx_ZERO_EXTEND (V2DImode,
	operand1),
	operand2)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2974 */
rtx
gen_aarch64_saddw2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2979 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
  emit_insn (gen_aarch64_saddw2v16qi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2974 */
rtx
gen_aarch64_saddw2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2979 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_saddw2v8hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2974 */
rtx
gen_aarch64_saddw2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2979 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_saddw2v4si_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2986 */
rtx
gen_aarch64_uaddw2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2991 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
  emit_insn (gen_aarch64_uaddw2v16qi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2986 */
rtx
gen_aarch64_uaddw2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2991 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_uaddw2v8hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2986 */
rtx
gen_aarch64_uaddw2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 2991 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_uaddw2v4si_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2999 */
rtx
gen_aarch64_ssubw2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3004 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
  emit_insn (gen_aarch64_ssubw2v16qi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2999 */
rtx
gen_aarch64_ssubw2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3004 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_ssubw2v8hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:2999 */
rtx
gen_aarch64_ssubw2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3004 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_ssubw2v4si_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3011 */
rtx
gen_aarch64_usubw2v16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3016 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V16QImode, true);
  emit_insn (gen_aarch64_usubw2v16qi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3011 */
rtx
gen_aarch64_usubw2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3016 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_usubw2v8hi_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3011 */
rtx
gen_aarch64_usubw2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3016 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_usubw2v4si_internal (operands[0], operands[1],
						operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3531 */
rtx
gen_aarch64_sqdmlal2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3537 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmlal2v8hi_internal (operands[0], operands[1],
						  operands[2], operands[3], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3531 */
rtx
gen_aarch64_sqdmlal2v4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3537 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmlal2v4si_internal (operands[0], operands[1],
						  operands[2], operands[3], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_sqdmlsl2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3550 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmlsl2v8hi_internal (operands[0], operands[1],
						  operands[2], operands[3], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3544 */
rtx
gen_aarch64_sqdmlsl2v4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3550 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmlsl2v4si_internal (operands[0], operands[1],
						  operands[2], operands[3], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3611 */
rtx
gen_aarch64_sqdmlal2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3618 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmlal2_lanev8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3611 */
rtx
gen_aarch64_sqdmlal2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3618 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmlal2_lanev4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3626 */
rtx
gen_aarch64_sqdmlal2_laneqv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3633 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmlal2_laneqv8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3626 */
rtx
gen_aarch64_sqdmlal2_laneqv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3633 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmlal2_laneqv4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3641 */
rtx
gen_aarch64_sqdmlsl2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3648 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmlsl2_lanev8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3641 */
rtx
gen_aarch64_sqdmlsl2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3648 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmlsl2_lanev4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3656 */
rtx
gen_aarch64_sqdmlsl2_laneqv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3663 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmlsl2_laneqv8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3656 */
rtx
gen_aarch64_sqdmlsl2_laneqv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[5];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3663 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmlsl2_laneqv4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       operands[4], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3690 */
rtx
gen_aarch64_sqdmlal2_nv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3696 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmlal2_nv8hi_internal (operands[0], operands[1],
						    operands[2], operands[3],
						    p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3690 */
rtx
gen_aarch64_sqdmlal2_nv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3696 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmlal2_nv4si_internal (operands[0], operands[1],
						    operands[2], operands[3],
						    p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3704 */
rtx
gen_aarch64_sqdmlsl2_nv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3710 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmlsl2_nv8hi_internal (operands[0], operands[1],
						    operands[2], operands[3],
						    p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3704 */
rtx
gen_aarch64_sqdmlsl2_nv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3710 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmlsl2_nv4si_internal (operands[0], operands[1],
						    operands[2], operands[3],
						    p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3859 */
rtx
gen_aarch64_sqdmull2v8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3864 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmull2v8hi_internal (operands[0], operands[1],
						  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3859 */
rtx
gen_aarch64_sqdmull2v4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3864 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmull2v4si_internal (operands[0], operands[1],
						  operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3919 */
rtx
gen_aarch64_sqdmull2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3925 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmull2_lanev8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3919 */
rtx
gen_aarch64_sqdmull2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3925 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmull2_lanev4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3933 */
rtx
gen_aarch64_sqdmull2_laneqv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3939 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmull2_laneqv8hi_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3933 */
rtx
gen_aarch64_sqdmull2_laneqv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3939 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmull2_laneqv4si_internal (operands[0], operands[1],
						       operands[2], operands[3],
						       p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3967 */
rtx
gen_aarch64_sqdmull2_nv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3972 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V8HImode, true);
  emit_insn (gen_aarch64_sqdmull2_nv8hi_internal (operands[0], operands[1],
						    operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:3967 */
rtx
gen_aarch64_sqdmull2_nv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 3972 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx p = aarch64_simd_vect_par_cnst_half (V4SImode, true);
  emit_insn (gen_aarch64_sqdmull2_nv4si_internal (operands[0], operands[1],
						    operands[2], p));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
extern rtx_insn *gen_split_50 (rtx_insn *, rtx *);
rtx_insn *
gen_split_50 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_50\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (LT, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (LT, operands[1], operands[2]);
	rtx comparison = gen_rtx_LT (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LT (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
extern rtx_insn *gen_split_51 (rtx_insn *, rtx *);
rtx_insn *
gen_split_51 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_51\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (LE, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (LE, operands[1], operands[2]);
	rtx comparison = gen_rtx_LE (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LE (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
extern rtx_insn *gen_split_52 (rtx_insn *, rtx *);
rtx_insn *
gen_split_52 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_52\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (EQ, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (EQ, operands[1], operands[2]);
	rtx comparison = gen_rtx_EQ (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_EQ (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
extern rtx_insn *gen_split_53 (rtx_insn *, rtx *);
rtx_insn *
gen_split_53 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_53\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (GE, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (GE, operands[1], operands[2]);
	rtx comparison = gen_rtx_GE (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GE (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4128 */
extern rtx_insn *gen_split_54 (rtx_insn *, rtx *);
rtx_insn *
gen_split_54 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_54\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = SELECT_CC_MODE (GT, operands[1], operands[2]);
	rtx cc_reg = aarch64_gen_compare_reg (GT, operands[1], operands[2]);
	rtx comparison = gen_rtx_GT (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GT (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4191 */
extern rtx_insn *gen_split_55 (rtx_insn *, rtx *);
rtx_insn *
gen_split_55 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_55\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4208 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = CCmode;
	rtx cc_reg = aarch64_gen_compare_reg (LTU, operands[1], operands[2]);
	rtx comparison = gen_rtx_LTU (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LTU (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4191 */
extern rtx_insn *gen_split_56 (rtx_insn *, rtx *);
rtx_insn *
gen_split_56 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_56\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4208 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = CCmode;
	rtx cc_reg = aarch64_gen_compare_reg (LEU, operands[1], operands[2]);
	rtx comparison = gen_rtx_LEU (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_LEU (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4191 */
extern rtx_insn *gen_split_57 (rtx_insn *, rtx *);
rtx_insn *
gen_split_57 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_57\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4208 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = CCmode;
	rtx cc_reg = aarch64_gen_compare_reg (GEU, operands[1], operands[2]);
	rtx comparison = gen_rtx_GEU (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GEU (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4191 */
extern rtx_insn *gen_split_58 (rtx_insn *, rtx *);
rtx_insn *
gen_split_58 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_58\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4208 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	machine_mode mode = CCmode;
	rtx cc_reg = aarch64_gen_compare_reg (GTU, operands[1], operands[2]);
	rtx comparison = gen_rtx_GTU (mode, operands[1], operands[2]);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_GTU (DImode,
	operand1,
	operand2))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4261 */
extern rtx_insn *gen_split_59 (rtx_insn *, rtx *);
rtx_insn *
gen_split_59 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_59\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4280 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    /* If we are in the general purpose register file,
       we split to a sequence of comparison and store.  */
    if (GP_REGNUM_P (REGNO (operands[0]))
	&& GP_REGNUM_P (REGNO (operands[1])))
      {
	rtx and_tree = gen_rtx_AND (DImode, operands[1], operands[2]);
	machine_mode mode = SELECT_CC_MODE (NE, and_tree, const0_rtx);
	rtx cc_reg = aarch64_gen_compare_reg (NE, and_tree, const0_rtx);
	rtx comparison = gen_rtx_NE (mode, and_tree, const0_rtx);
	emit_insn (gen_cstoredi_neg (operands[0], comparison, cc_reg));
	DONE;
      }
    /* Otherwise, we expand to a similar pattern which does not
       clobber CC_REGNUM.  */
  }
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_NEG (DImode,
	gen_rtx_NE (DImode,
	gen_rtx_AND (DImode,
	operand1,
	operand2),
	const0_rtx))));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4371 */
rtx
gen_sqrtv4hf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv4hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4375 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V4HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4371 */
rtx
gen_sqrtv8hf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv8hf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4375 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V8HFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4371 */
rtx
gen_sqrtv2sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv2sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4375 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V2SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4371 */
rtx
gen_sqrtv4sf2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv4sf2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4375 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V4SFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4371 */
rtx
gen_sqrtv2df2 (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"sqrtv2df2 cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4375 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_emit_approx_sqrt (operands[0], operands[1], false))
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_SQRT (V2DFmode,
	operand1)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4425 */
rtx
gen_vec_load_lanesoiv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4431 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V16QImode);
      emit_insn (gen_aarch64_simd_ld2v16qi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4425 */
rtx
gen_vec_load_lanesoiv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4431 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V8HImode);
      emit_insn (gen_aarch64_simd_ld2v8hi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4425 */
rtx
gen_vec_load_lanesoiv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4431 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V4SImode);
      emit_insn (gen_aarch64_simd_ld2v4si (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4425 */
rtx
gen_vec_load_lanesoiv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4431 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V2DImode);
      emit_insn (gen_aarch64_simd_ld2v2di (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4425 */
rtx
gen_vec_load_lanesoiv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4431 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V8HFmode);
      emit_insn (gen_aarch64_simd_ld2v8hf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4425 */
rtx
gen_vec_load_lanesoiv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4431 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V4SFmode);
      emit_insn (gen_aarch64_simd_ld2v4sf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4425 */
rtx
gen_vec_load_lanesoiv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesoiv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4431 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V2DFmode);
      emit_insn (gen_aarch64_simd_ld2v2df (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistoi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld2v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	28)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4469 */
rtx
gen_vec_store_lanesoiv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4475 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V16QImode);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v16qi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4469 */
rtx
gen_vec_store_lanesoiv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4475 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V8HImode);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v8hi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4469 */
rtx
gen_vec_store_lanesoiv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4475 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V4SImode);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v4si (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4469 */
rtx
gen_vec_store_lanesoiv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4475 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V2DImode);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v2di (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4469 */
rtx
gen_vec_store_lanesoiv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4475 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V8HFmode);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v8hf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4469 */
rtx
gen_vec_store_lanesoiv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4475 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V4SFmode);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v4sf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4469 */
rtx
gen_vec_store_lanesoiv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesoiv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4475 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (OImode);
      rtx mask = aarch64_reverse_mask (V2DFmode);
      emit_insn (gen_aarch64_rev_reglistoi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st2v2df (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st2v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (OImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	47)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4523 */
rtx
gen_vec_load_lanesciv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4529 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V16QImode);
      emit_insn (gen_aarch64_simd_ld3v16qi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4523 */
rtx
gen_vec_load_lanesciv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4529 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V8HImode);
      emit_insn (gen_aarch64_simd_ld3v8hi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4523 */
rtx
gen_vec_load_lanesciv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4529 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V4SImode);
      emit_insn (gen_aarch64_simd_ld3v4si (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4523 */
rtx
gen_vec_load_lanesciv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4529 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V2DImode);
      emit_insn (gen_aarch64_simd_ld3v2di (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4523 */
rtx
gen_vec_load_lanesciv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4529 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V8HFmode);
      emit_insn (gen_aarch64_simd_ld3v8hf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4523 */
rtx
gen_vec_load_lanesciv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4529 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V4SFmode);
      emit_insn (gen_aarch64_simd_ld3v4sf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4523 */
rtx
gen_vec_load_lanesciv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesciv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4529 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V2DFmode);
      emit_insn (gen_aarch64_simd_ld3v2df (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistci (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld3v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	30)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4567 */
rtx
gen_vec_store_lanesciv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4573 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V16QImode);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v16qi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4567 */
rtx
gen_vec_store_lanesciv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4573 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V8HImode);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v8hi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4567 */
rtx
gen_vec_store_lanesciv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4573 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V4SImode);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v4si (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4567 */
rtx
gen_vec_store_lanesciv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4573 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V2DImode);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v2di (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4567 */
rtx
gen_vec_store_lanesciv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4573 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V8HFmode);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v8hf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4567 */
rtx
gen_vec_store_lanesciv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4573 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V4SFmode);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v4sf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4567 */
rtx
gen_vec_store_lanesciv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesciv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4573 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (CImode);
      rtx mask = aarch64_reverse_mask (V2DFmode);
      emit_insn (gen_aarch64_rev_reglistci (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st3v2df (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st3v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (CImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	48)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4621 */
rtx
gen_vec_load_lanesxiv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V16QImode);
      emit_insn (gen_aarch64_simd_ld4v16qi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4621 */
rtx
gen_vec_load_lanesxiv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V8HImode);
      emit_insn (gen_aarch64_simd_ld4v8hi (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4621 */
rtx
gen_vec_load_lanesxiv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V4SImode);
      emit_insn (gen_aarch64_simd_ld4v4si (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4621 */
rtx
gen_vec_load_lanesxiv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V2DImode);
      emit_insn (gen_aarch64_simd_ld4v2di (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4621 */
rtx
gen_vec_load_lanesxiv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V8HFmode);
      emit_insn (gen_aarch64_simd_ld4v8hf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4621 */
rtx
gen_vec_load_lanesxiv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V4SFmode);
      emit_insn (gen_aarch64_simd_ld4v4sf (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4621 */
rtx
gen_vec_load_lanesxiv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_load_lanesxiv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4627 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V2DFmode);
      emit_insn (gen_aarch64_simd_ld4v2df (tmp, operands[1]));
      emit_insn (gen_aarch64_rev_reglistxi (operands[0], tmp, mask));
    }
  else
    emit_insn (gen_aarch64_simd_ld4v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	32)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4665 */
rtx
gen_vec_store_lanesxiv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv16qi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4671 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V16QImode);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v16qi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v16qi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4665 */
rtx
gen_vec_store_lanesxiv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv8hi cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4671 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V8HImode);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v8hi (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v8hi (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4665 */
rtx
gen_vec_store_lanesxiv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv4si cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4671 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V4SImode);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v4si (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v4si (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4665 */
rtx
gen_vec_store_lanesxiv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv2di cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4671 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V2DImode);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v2di (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v2di (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4665 */
rtx
gen_vec_store_lanesxiv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv8hf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4671 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V8HFmode);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v8hf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v8hf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4665 */
rtx
gen_vec_store_lanesxiv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv4sf cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4671 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V4SFmode);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v4sf (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v4sf (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4665 */
rtx
gen_vec_store_lanesxiv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL _Pragma ("GCC error \"vec_store_lanesxiv2df cannot FAIL\"") (void)0
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4671 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (BYTES_BIG_ENDIAN)
    {
      rtx tmp = gen_reg_rtx (XImode);
      rtx mask = aarch64_reverse_mask (V2DFmode);
      emit_insn (gen_aarch64_rev_reglistxi (tmp, operands[1], mask));
      emit_insn (gen_aarch64_simd_st4v2df (operands[0], tmp));
    }
  else
    emit_insn (gen_aarch64_simd_st4v2df (operands[0], operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	gen_rtx_UNSPEC (XImode,
	gen_rtvec (2,
		operand1,
		gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61)),
	49)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4684 */
extern rtx_insn *gen_split_60 (rtx_insn *, rtx *);
rtx_insn *
gen_split_60 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_60\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4694 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int i;
  int nregs = GET_MODE_SIZE (OImode) / UNITS_PER_VREG;
  for (i = 0; i < nregs; i++)
    {
      rtx op0 = gen_rtx_REG (V16QImode, REGNO (operands[0]) + i);
      rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]) + i);
      emit_insn (gen_aarch64_tbl1v16qi (op0, op1, operands[2]));
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4684 */
extern rtx_insn *gen_split_61 (rtx_insn *, rtx *);
rtx_insn *
gen_split_61 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_61\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4694 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int i;
  int nregs = GET_MODE_SIZE (CImode) / UNITS_PER_VREG;
  for (i = 0; i < nregs; i++)
    {
      rtx op0 = gen_rtx_REG (V16QImode, REGNO (operands[0]) + i);
      rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]) + i);
      emit_insn (gen_aarch64_tbl1v16qi (op0, op1, operands[2]));
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4684 */
extern rtx_insn *gen_split_62 (rtx_insn *, rtx *);
rtx_insn *
gen_split_62 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_62\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4694 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int i;
  int nregs = GET_MODE_SIZE (XImode) / UNITS_PER_VREG;
  for (i = 0; i < nregs; i++)
    {
      rtx op0 = gen_rtx_REG (V16QImode, REGNO (operands[0]) + i);
      rtx op1 = gen_rtx_REG (V16QImode, REGNO (operands[1]) + i);
      emit_insn (gen_aarch64_tbl1v16qi (op0, op1, operands[2]));
    }
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4711 */
rtx
gen_movoi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4715 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (can_create_pseudo_p ())
    {
      if (GET_CODE (operands[0]) != REG)
	operands[1] = force_reg (OImode, operands[1]);
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4711 */
rtx
gen_movci (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4715 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (can_create_pseudo_p ())
    {
      if (GET_CODE (operands[0]) != REG)
	operands[1] = force_reg (CImode, operands[1]);
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4711 */
rtx
gen_movxi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4715 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (can_create_pseudo_p ())
    {
      if (GET_CODE (operands[0]) != REG)
	operands[1] = force_reg (XImode, operands[1]);
    }
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand0,
	operand1));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4793 */
extern rtx_insn *gen_split_63 (rtx_insn *, rtx *);
rtx_insn *
gen_split_63 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_63\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4798 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_simd_emit_reg_reg_move (operands, TImode, 2);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4803 */
extern rtx_insn *gen_split_64 (rtx_insn *, rtx *);
rtx_insn *
gen_split_64 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_64\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4808 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (register_operand (operands[0], CImode)
      && register_operand (operands[1], CImode))
    {
      aarch64_simd_emit_reg_reg_move (operands, TImode, 3);
      DONE;
    }
  else if (BYTES_BIG_ENDIAN)
    {
      emit_move_insn (simplify_gen_subreg (OImode, operands[0], CImode, 0),
		      simplify_gen_subreg (OImode, operands[1], CImode, 0));
      emit_move_insn (gen_lowpart (V16QImode,
				   simplify_gen_subreg (TImode, operands[0],
							CImode, 32)),
		      gen_lowpart (V16QImode,
				   simplify_gen_subreg (TImode, operands[1],
							CImode, 32)));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4831 */
extern rtx_insn *gen_split_65 (rtx_insn *, rtx *);
rtx_insn *
gen_split_65 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_65\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4836 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (register_operand (operands[0], XImode)
      && register_operand (operands[1], XImode))
    {
      aarch64_simd_emit_reg_reg_move (operands, TImode, 4);
      DONE;
    }
  else if (BYTES_BIG_ENDIAN)
    {
      emit_move_insn (simplify_gen_subreg (OImode, operands[0], XImode, 0),
		      simplify_gen_subreg (OImode, operands[1], XImode, 0));
      emit_move_insn (simplify_gen_subreg (OImode, operands[0], XImode, 32),
		      simplify_gen_subreg (OImode, operands[1], XImode, 32));
      DONE;
    }
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv8qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv16qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv4hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv8hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv2si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv4si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv2di (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv4hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv8hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv2sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv4sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rv2df (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rdi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld2rdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 2);

  emit_insn (gen_aarch64_simd_ld2rdf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv8qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv16qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv4hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv8hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv2si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv4si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv2di (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv4hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv8hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv2sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv4sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rv2df (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rdi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld3rdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 3);

  emit_insn (gen_aarch64_simd_ld3rdf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv8qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv16qi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv4hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv8hi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv2si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv4si (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv2di (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv4hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv8hf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv2sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv4sf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rv2df (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rdi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rdi (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:4855 */
rtx
gen_aarch64_ld4rdf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 4860 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 4);

  emit_insn (gen_aarch64_simd_ld4rdf (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld2v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld2v8qi_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld2v8qi_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld2v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld2v4hi_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld2v4hi_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld2v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld2v4hf_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld2v4hf_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld2v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld2v2si_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld2v2si_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld2v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld2v2sf_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld2v2sf_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld2di_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld2di_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 2 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld2df_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld2df_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld3v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld3v8qi_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld3v8qi_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld3v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld3v4hi_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld3v4hi_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld3v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld3v4hf_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld3v4hf_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld3v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld3v2si_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld3v2si_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld3v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld3v2sf_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld3v2sf_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld3di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld3di_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld3di_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld3df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 3 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld3df_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld3df_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld4v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld4v8qi_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld4v8qi_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld4v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld4v4hi_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld4v4hi_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld4v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld4v4hf_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld4v4hf_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld4v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld4v2si_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld4v2si_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld4v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld4v2sf_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld4v2sf_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld4di_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld4di_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5146 */
rtx
gen_aarch64_ld4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5151 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, 4 * 8);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_ld4df_dreg_be (operands[0],
								mem));
  else
    emit_insn (gen_aarch64_ld4df_dreg_le (operands[0],
								mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8QImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v8qi (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V16QImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v16qi (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4HImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v4hi (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8HImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v8hi (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2SImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v2si (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4SImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v4si (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2DImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v2di (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4HFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v4hf (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8HFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v8hf (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2SFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v2sf (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4SFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v4sf (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5164 */
rtx
gen_aarch64_ld1v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5168 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2DFmode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_ld1v2df (operands[0], mem));
  else
    emit_move_insn (operands[0], mem);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld2v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v16qi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld2v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v8hi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld2v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v4si (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld2v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v2di (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld2v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v8hf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld2v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v4sf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld2v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld2v2df (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld3v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v16qi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld3v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v8hi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld3v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v4si (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld3v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v2di (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld3v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v8hf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld3v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v4sf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld3v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld3v2df (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld4v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v16qi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld4v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v8hi (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld4v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v4si (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld4v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v2di (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld4v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v8hf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld4v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v4sf (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5179 */
rtx
gen_aarch64_ld4v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5184 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[1]);

  emit_insn (gen_aarch64_simd_ld4v2df (operands[0], mem));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8QImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev8qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V16QImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev16qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4HImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev4hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8HImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev8hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2SImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev2si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4SImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev4si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2DImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev2di (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4HFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev4hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8HFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev8hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2SFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev2sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4SFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev4sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2DFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanev2df (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (DImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanedi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld2_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 2);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (DFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesoi_lanedf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8QImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev8qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V16QImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev16qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4HImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev4hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8HImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev8hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2SImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev2si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4SImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev4si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2DImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev2di (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4HFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev4hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8HFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev8hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2SFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev2sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4SFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev4sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2DFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanev2df (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (DImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanedi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld3_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 3);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (DFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesci_lanedf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8QImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev8qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V16QImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev16qi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4HImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev4hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8HImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev8hi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2SImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev2si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4SImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev4si (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2DImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev2di (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4HFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev4hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V8HFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev8hf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2SFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev2sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V4SFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev4sf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (V2DFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanev2df (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (DImode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanedi (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5192 */
rtx
gen_aarch64_ld4_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5199 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 4);

  aarch64_simd_lane_bounds (operands[3], 0,
			    GET_MODE_NUNITS (DFmode),
			    NULL);
  emit_insn (gen_aarch64_vec_load_lanesxi_lanedf (
	operands[0], mem, operands[2], operands[3]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregoiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V16QImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V16QImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V8QImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregoiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregoiv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregoiv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregoiv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregoidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregoidf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregciv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V16QImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V16QImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V8QImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregciv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregciv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregciv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregciv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregcidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregcidf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregxiv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V16QImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V16QImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V8QImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregxiv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregxiv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V8HFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V4HFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregxiv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregxiv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V4SFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (V2SFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregxidi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DImode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DImode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DImode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5217 */
rtx
gen_aarch64_get_dregxidf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5222 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  rtx temp = gen_reg_rtx (V2DFmode);
  int offset = part * 16;

  emit_move_insn (temp, gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  emit_move_insn (operands[0], gen_lowpart (DFmode, temp));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregoiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V16QImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregoiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregoiv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregoiv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregoiv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregoiv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregoiv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregciv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V16QImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregciv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregciv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregciv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregciv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregciv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregciv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregxiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V16QImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregxiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregxiv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregxiv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DImode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregxiv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V8HFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregxiv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V4SFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5234 */
rtx
gen_aarch64_get_qregxiv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5239 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[2]);
  int offset = part * 16;

  emit_move_insn (operands[0],
		  gen_rtx_SUBREG (V2DFmode, operands[1], offset));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv4hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv2si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv4hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv2sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5254 */
rtx
gen_vec_perm_constv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5260 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  if (aarch64_expand_vec_perm_const (operands[0], operands[1],
				     operands[2], operands[3]))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5268 */
rtx
gen_vec_permv8qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vec_perm (operands[0], operands[1],
			   operands[2], operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5268 */
rtx
gen_vec_permv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5274 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vec_perm (operands[0], operands[1],
			   operands[2], operands[3]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5369 */
extern rtx_insn *gen_split_66 (rtx_insn *, rtx *);
rtx_insn *
gen_split_66 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_66\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5378 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_split_combinev16qi (operands);
  DONE;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st2v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v8qi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st2v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v4hi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st2v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v4hf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st2v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v2si_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st2v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2v2sf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2di_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 2 * 8);

  emit_insn (gen_aarch64_st2df_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st3v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v8qi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st3v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v4hi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st3v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v4hf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st3v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v2si_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st3v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3v2sf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st3di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3di_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st3df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 3 * 8);

  emit_insn (gen_aarch64_st3df_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st4v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v8qi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st4v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v4hi_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st4v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v4hf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st4v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v2si_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st4v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4v2sf_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st4di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4di_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5480 */
rtx
gen_aarch64_st4df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5485 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, 4 * 8);

  emit_insn (gen_aarch64_st4df_dreg (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st2v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v16qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st2v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v8hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st2v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v4si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st2v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v2di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st2v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v8hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st2v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v4sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st2v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = OImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st2v2df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st3v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v16qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st3v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v8hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st3v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v4si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st3v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v2di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st3v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v8hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st3v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v4sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st3v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = CImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st3v2df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st4v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v16qi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st4v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v8hi (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st4v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v4si (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st4v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v2di (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st4v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v8hf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st4v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v4sf (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5493 */
rtx
gen_aarch64_st4v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5498 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = XImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  emit_insn (gen_aarch64_simd_st4v2df (mem, operands[1]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev8qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev16qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev4hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev8hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev2si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev4si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev2di (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev4hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev8hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev2sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev4sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanev2df (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanedi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st2_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 2);

  emit_insn (gen_aarch64_vec_store_lanesoi_lanedf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev8qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev16qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev4hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev8hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev2si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev4si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev2di (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev4hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev8hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev2sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev4sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanev2df (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanedi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st3_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 3);

  emit_insn (gen_aarch64_vec_store_lanesci_lanedf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8QImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev8qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V16QImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev16qi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V16QImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev4hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev8hi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev2si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev4si (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev2di (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4HFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev4hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V8HFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev8hf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V8HFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2SFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev2sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V4SFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev4sf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V4SFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanev2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (V2DFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanev2df (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (V2DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanedi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DImode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanedi (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DImode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5506 */
rtx
gen_aarch64_st4_lanedf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5512 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (DFmode))
		     * 4);

  emit_insn (gen_aarch64_vec_store_lanesxi_lanedf (
		mem, operands[1], operands[2]));
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_UNSPEC (DFmode,
	gen_rtvec (1,
		const0_rtx),
	61));
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8QImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v8qi (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V16QImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v16qi (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4HImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v4hi (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8HImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v8hi (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2SImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v2si (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4SImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v4si (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2DImode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v2di (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4HFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v4hf (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V8HFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v8hf (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2SFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v2sf (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V4SFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v4sf (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5522 */
rtx
gen_aarch64_st1v2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5526 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  machine_mode mode = V2DFmode;
  rtx mem = gen_rtx_MEM (mode, operands[0]);

  if (BYTES_BIG_ENDIAN)
    emit_insn (gen_aarch64_be_st1v2df (mem, operands[1]));
  else
    emit_move_insn (mem, operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregoiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V16QImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregoiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregoiv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregoiv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregoiv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregoiv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregoiv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregciv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V16QImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregciv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregciv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregciv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregciv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregciv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregciv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregxiv16qi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V16QImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregxiv8hi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregxiv4si (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregxiv2di (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DImode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregxiv8hf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V8HFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregxiv4sf (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V4SFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5543 */
rtx
gen_aarch64_set_qregxiv2df (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5549 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  int part = INTVAL (operands[3]);
  int offset = part * 16;

  emit_move_insn (operands[0], operands[1]);
  emit_move_insn (gen_rtx_SUBREG (V2DFmode, operands[0], offset),
		  operands[2]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv8qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv16qi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv4hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv8hi (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv2si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv4si (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv2di (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv4hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv8hf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv2sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv4sf (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5561 */
rtx
gen_vec_initv2df (rtx operand0,
	rtx operand1)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
    operands[1] = operand1;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5565 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
  aarch64_expand_vector_init (operands[0], operands[1]);
  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit (operand0, true);
  emit (operand1, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv8qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev8qi (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv16qi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev16qi (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv4hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev4hi (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv8hi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev8hi (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv2si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev2si (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv4si (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev4si (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv2di (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev2di (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv4hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev4hf (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv8hf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev8hf (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv2sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev2sf (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv4sf (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev4sf (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md:5618 */
rtx
gen_vec_extractv2df (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 5623 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-simd.md"
{
    emit_insn
      (gen_aarch64_get_lanev2df (operands[0], operands[1], operands[2]));
    DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:23 */
rtx
gen_atomic_compare_and_swapqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 33 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_expand_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:23 */
rtx
gen_atomic_compare_and_swaphi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 33 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_expand_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:23 */
rtx
gen_atomic_compare_and_swapsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 33 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_expand_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:23 */
rtx
gen_atomic_compare_and_swapdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3,
	rtx operand4,
	rtx operand5,
	rtx operand6,
	rtx operand7)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[8];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
    operands[4] = operand4;
    operands[5] = operand5;
    operands[6] = operand6;
    operands[7] = operand7;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 33 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_expand_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
    operand4 = operands[4];
    (void) operand4;
    operand5 = operands[5];
    (void) operand5;
    operand6 = operands[6];
    (void) operand6;
    operand7 = operands[7];
    (void) operand7;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, true);
  emit (operand4, true);
  emit (operand5, true);
  emit (operand6, true);
  emit (operand7, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:39 */
extern rtx_insn *gen_split_67 (rtx_insn *, rtx *);
rtx_insn *
gen_split_67 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_67\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 58 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:39 */
extern rtx_insn *gen_split_68 (rtx_insn *, rtx *);
rtx_insn *
gen_split_68 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_68\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 58 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:64 */
extern rtx_insn *gen_split_69 (rtx_insn *, rtx *);
rtx_insn *
gen_split_69 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_69\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 82 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:64 */
extern rtx_insn *gen_split_70 (rtx_insn *, rtx *);
rtx_insn *
gen_split_70 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_70\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 82 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_compare_and_swap (operands);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:88 */
extern rtx_insn *gen_split_71 (rtx_insn *, rtx *);
rtx_insn *
gen_split_71 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_71\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 106 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_cas (operands[0], operands[1],
			    operands[2], operands[3],
			    operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:88 */
extern rtx_insn *gen_split_72 (rtx_insn *, rtx *);
rtx_insn *
gen_split_72 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_72\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 106 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_cas (operands[0], operands[1],
			    operands[2], operands[3],
			    operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:114 */
extern rtx_insn *gen_split_73 (rtx_insn *, rtx *);
rtx_insn *
gen_split_73 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_73\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 131 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_cas (operands[0], operands[1],
			    operands[2], operands[3],
			    operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:114 */
extern rtx_insn *gen_split_74 (rtx_insn *, rtx *);
rtx_insn *
gen_split_74 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_74\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 131 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_cas (operands[0], operands[1],
			    operands[2], operands[3],
			    operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:139 */
rtx
gen_atomic_exchangeqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx, rtx);

    /* Use an atomic SWP when available.  */
    if (TARGET_LSE)
      gen = gen_aarch64_atomic_exchangeqi_lse;
    else
      gen = gen_aarch64_atomic_exchangeqi;

    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:139 */
rtx
gen_atomic_exchangehi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx, rtx);

    /* Use an atomic SWP when available.  */
    if (TARGET_LSE)
      gen = gen_aarch64_atomic_exchangehi_lse;
    else
      gen = gen_aarch64_atomic_exchangehi;

    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:139 */
rtx
gen_atomic_exchangesi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx, rtx);

    /* Use an atomic SWP when available.  */
    if (TARGET_LSE)
      gen = gen_aarch64_atomic_exchangesi_lse;
    else
      gen = gen_aarch64_atomic_exchangesi;

    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:139 */
rtx
gen_atomic_exchangedi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 145 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx, rtx);

    /* Use an atomic SWP when available.  */
    if (TARGET_LSE)
      gen = gen_aarch64_atomic_exchangedi_lse;
    else
      gen = gen_aarch64_atomic_exchangedi;

    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit (operand2, true);
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:160 */
extern rtx_insn *gen_split_75 (rtx_insn *, rtx *);
rtx_insn *
gen_split_75 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_75\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 174 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:160 */
extern rtx_insn *gen_split_76 (rtx_insn *, rtx *);
rtx_insn *
gen_split_76 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_76\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 174 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:160 */
extern rtx_insn *gen_split_77 (rtx_insn *, rtx *);
rtx_insn *
gen_split_77 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_77\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 174 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:160 */
extern rtx_insn *gen_split_78 (rtx_insn *, rtx *);
rtx_insn *
gen_split_78 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_78\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 174 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:181 */
extern rtx_insn *gen_split_79 (rtx_insn *, rtx *);
rtx_insn *
gen_split_79 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_79\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 193 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:181 */
extern rtx_insn *gen_split_80 (rtx_insn *, rtx *);
rtx_insn *
gen_split_80 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_80\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 193 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:181 */
extern rtx_insn *gen_split_81 (rtx_insn *, rtx *);
rtx_insn *
gen_split_81 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_81\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 193 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:181 */
extern rtx_insn *gen_split_82 (rtx_insn *, rtx *);
rtx_insn *
gen_split_82 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_82\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 193 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (SET, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_addqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (PLUS))
      gen = gen_aarch64_atomic_addqi_lse;
    else
      gen = gen_aarch64_atomic_addqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_subqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (MINUS))
      gen = gen_aarch64_atomic_subqi_lse;
    else
      gen = gen_aarch64_atomic_subqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_orqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (IOR))
      gen = gen_aarch64_atomic_orqi_lse;
    else
      gen = gen_aarch64_atomic_orqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_xorqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (XOR))
      gen = gen_aarch64_atomic_xorqi_lse;
    else
      gen = gen_aarch64_atomic_xorqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_andqi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (AND))
      gen = gen_aarch64_atomic_andqi_lse;
    else
      gen = gen_aarch64_atomic_andqi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (QImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_addhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (PLUS))
      gen = gen_aarch64_atomic_addhi_lse;
    else
      gen = gen_aarch64_atomic_addhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_subhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (MINUS))
      gen = gen_aarch64_atomic_subhi_lse;
    else
      gen = gen_aarch64_atomic_subhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_orhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (IOR))
      gen = gen_aarch64_atomic_orhi_lse;
    else
      gen = gen_aarch64_atomic_orhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_xorhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (XOR))
      gen = gen_aarch64_atomic_xorhi_lse;
    else
      gen = gen_aarch64_atomic_xorhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_andhi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (AND))
      gen = gen_aarch64_atomic_andhi_lse;
    else
      gen = gen_aarch64_atomic_andhi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (HImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_addsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (PLUS))
      gen = gen_aarch64_atomic_addsi_lse;
    else
      gen = gen_aarch64_atomic_addsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_subsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (MINUS))
      gen = gen_aarch64_atomic_subsi_lse;
    else
      gen = gen_aarch64_atomic_subsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_orsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (IOR))
      gen = gen_aarch64_atomic_orsi_lse;
    else
      gen = gen_aarch64_atomic_orsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_xorsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (XOR))
      gen = gen_aarch64_atomic_xorsi_lse;
    else
      gen = gen_aarch64_atomic_xorsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_andsi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (AND))
      gen = gen_aarch64_atomic_andsi_lse;
    else
      gen = gen_aarch64_atomic_andsi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (SImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_adddi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (PLUS))
      gen = gen_aarch64_atomic_adddi_lse;
    else
      gen = gen_aarch64_atomic_adddi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_subdi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (MINUS))
      gen = gen_aarch64_atomic_subdi_lse;
    else
      gen = gen_aarch64_atomic_subdi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_ordi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (IOR))
      gen = gen_aarch64_atomic_ordi_lse;
    else
      gen = gen_aarch64_atomic_ordi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_xordi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (XOR))
      gen = gen_aarch64_atomic_xordi_lse;
    else
      gen = gen_aarch64_atomic_xordi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:200 */
rtx
gen_atomic_anddi (rtx operand0,
	rtx operand1,
	rtx operand2)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[3];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 206 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    rtx (*gen) (rtx, rtx, rtx);

    /* Use an atomic load-operate instruction when possible.  */
    if (aarch64_atomic_ldop_supported_p (AND))
      gen = gen_aarch64_atomic_anddi_lse;
    else
      gen = gen_aarch64_atomic_anddi;

    emit_insn (gen (operands[0], operands[1], operands[2]));

    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (DImode,
	operand1,
	operand2));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_83 (rtx_insn *, rtx *);
rtx_insn *
gen_split_83 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_83\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_84 (rtx_insn *, rtx *);
rtx_insn *
gen_split_84 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_84\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_85 (rtx_insn *, rtx *);
rtx_insn *
gen_split_85 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_85\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_86 (rtx_insn *, rtx *);
rtx_insn *
gen_split_86 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_86\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_87 (rtx_insn *, rtx *);
rtx_insn *
gen_split_87 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_87\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_88 (rtx_insn *, rtx *);
rtx_insn *
gen_split_88 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_88\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_89 (rtx_insn *, rtx *);
rtx_insn *
gen_split_89 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_89\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_90 (rtx_insn *, rtx *);
rtx_insn *
gen_split_90 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_90\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_91 (rtx_insn *, rtx *);
rtx_insn *
gen_split_91 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_91\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_92 (rtx_insn *, rtx *);
rtx_insn *
gen_split_92 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_92\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_93 (rtx_insn *, rtx *);
rtx_insn *
gen_split_93 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_93\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_94 (rtx_insn *, rtx *);
rtx_insn *
gen_split_94 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_94\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_95 (rtx_insn *, rtx *);
rtx_insn *
gen_split_95 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_95\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_96 (rtx_insn *, rtx *);
rtx_insn *
gen_split_96 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_96\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_97 (rtx_insn *, rtx *);
rtx_insn *
gen_split_97 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_97\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_98 (rtx_insn *, rtx *);
rtx_insn *
gen_split_98 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_98\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_99 (rtx_insn *, rtx *);
rtx_insn *
gen_split_99 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_99\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_100 (rtx_insn *, rtx *);
rtx_insn *
gen_split_100 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_100\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_101 (rtx_insn *, rtx *);
rtx_insn *
gen_split_101 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_101\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:221 */
extern rtx_insn *gen_split_102 (rtx_insn *, rtx *);
rtx_insn *
gen_split_102 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_102\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 235 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_103 (rtx_insn *, rtx *);
rtx_insn *
gen_split_103 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_103\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_104 (rtx_insn *, rtx *);
rtx_insn *
gen_split_104 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_104\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_105 (rtx_insn *, rtx *);
rtx_insn *
gen_split_105 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_105\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_106 (rtx_insn *, rtx *);
rtx_insn *
gen_split_106 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_106\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_107 (rtx_insn *, rtx *);
rtx_insn *
gen_split_107 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_107\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_108 (rtx_insn *, rtx *);
rtx_insn *
gen_split_108 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_108\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_109 (rtx_insn *, rtx *);
rtx_insn *
gen_split_109 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_109\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_110 (rtx_insn *, rtx *);
rtx_insn *
gen_split_110 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_110\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_111 (rtx_insn *, rtx *);
rtx_insn *
gen_split_111 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_111\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_112 (rtx_insn *, rtx *);
rtx_insn *
gen_split_112 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_112\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_113 (rtx_insn *, rtx *);
rtx_insn *
gen_split_113 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_113\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_114 (rtx_insn *, rtx *);
rtx_insn *
gen_split_114 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_114\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_115 (rtx_insn *, rtx *);
rtx_insn *
gen_split_115 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_115\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_116 (rtx_insn *, rtx *);
rtx_insn *
gen_split_116 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_116\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_117 (rtx_insn *, rtx *);
rtx_insn *
gen_split_117 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_117\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_118 (rtx_insn *, rtx *);
rtx_insn *
gen_split_118 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_118\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_119 (rtx_insn *, rtx *);
rtx_insn *
gen_split_119 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_119\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_120 (rtx_insn *, rtx *);
rtx_insn *
gen_split_120 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_120\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_121 (rtx_insn *, rtx *);
rtx_insn *
gen_split_121 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_121\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:242 */
extern rtx_insn *gen_split_122 (rtx_insn *, rtx *);
rtx_insn *
gen_split_122 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_122\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 254 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[3], NULL, operands[0],
			     operands[1], operands[2]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:261 */
extern rtx_insn *gen_split_123 (rtx_insn *, rtx *);
rtx_insn *
gen_split_123 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_123\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 276 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
     aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:261 */
extern rtx_insn *gen_split_124 (rtx_insn *, rtx *);
rtx_insn *
gen_split_124 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_124\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 276 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
     aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:261 */
extern rtx_insn *gen_split_125 (rtx_insn *, rtx *);
rtx_insn *
gen_split_125 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_125\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 276 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
     aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:261 */
extern rtx_insn *gen_split_126 (rtx_insn *, rtx *);
rtx_insn *
gen_split_126 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_126\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 276 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
     aarch64_split_atomic_op (NOT, NULL, operands[3], operands[0],
			     operands[1], operands[2], operands[4]);
     DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_addqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (PLUS))
    gen = gen_aarch64_atomic_fetch_addqi_lse;
  else
    gen = gen_aarch64_atomic_fetch_addqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_PLUS (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_subqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (MINUS))
    gen = gen_aarch64_atomic_fetch_subqi_lse;
  else
    gen = gen_aarch64_atomic_fetch_subqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_MINUS (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_orqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (IOR))
    gen = gen_aarch64_atomic_fetch_orqi_lse;
  else
    gen = gen_aarch64_atomic_fetch_orqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_IOR (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_xorqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (XOR))
    gen = gen_aarch64_atomic_fetch_xorqi_lse;
  else
    gen = gen_aarch64_atomic_fetch_xorqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_XOR (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_andqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (AND))
    gen = gen_aarch64_atomic_fetch_andqi_lse;
  else
    gen = gen_aarch64_atomic_fetch_andqi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_AND (QImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_addhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (PLUS))
    gen = gen_aarch64_atomic_fetch_addhi_lse;
  else
    gen = gen_aarch64_atomic_fetch_addhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_PLUS (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_subhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (MINUS))
    gen = gen_aarch64_atomic_fetch_subhi_lse;
  else
    gen = gen_aarch64_atomic_fetch_subhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_MINUS (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_orhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (IOR))
    gen = gen_aarch64_atomic_fetch_orhi_lse;
  else
    gen = gen_aarch64_atomic_fetch_orhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_IOR (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_xorhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (XOR))
    gen = gen_aarch64_atomic_fetch_xorhi_lse;
  else
    gen = gen_aarch64_atomic_fetch_xorhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_XOR (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_andhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (AND))
    gen = gen_aarch64_atomic_fetch_andhi_lse;
  else
    gen = gen_aarch64_atomic_fetch_andhi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_AND (HImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_addsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (PLUS))
    gen = gen_aarch64_atomic_fetch_addsi_lse;
  else
    gen = gen_aarch64_atomic_fetch_addsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_PLUS (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_subsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (MINUS))
    gen = gen_aarch64_atomic_fetch_subsi_lse;
  else
    gen = gen_aarch64_atomic_fetch_subsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_MINUS (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_orsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (IOR))
    gen = gen_aarch64_atomic_fetch_orsi_lse;
  else
    gen = gen_aarch64_atomic_fetch_orsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_IOR (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_xorsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (XOR))
    gen = gen_aarch64_atomic_fetch_xorsi_lse;
  else
    gen = gen_aarch64_atomic_fetch_xorsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_XOR (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_andsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (AND))
    gen = gen_aarch64_atomic_fetch_andsi_lse;
  else
    gen = gen_aarch64_atomic_fetch_andsi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_AND (SImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_adddi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (PLUS))
    gen = gen_aarch64_atomic_fetch_adddi_lse;
  else
    gen = gen_aarch64_atomic_fetch_adddi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_PLUS (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_subdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (MINUS))
    gen = gen_aarch64_atomic_fetch_subdi_lse;
  else
    gen = gen_aarch64_atomic_fetch_subdi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_MINUS (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_ordi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (IOR))
    gen = gen_aarch64_atomic_fetch_ordi_lse;
  else
    gen = gen_aarch64_atomic_fetch_ordi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_IOR (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_xordi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (XOR))
    gen = gen_aarch64_atomic_fetch_xordi_lse;
  else
    gen = gen_aarch64_atomic_fetch_xordi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_XOR (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:285 */
rtx
gen_atomic_fetch_anddi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 292 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (AND))
    gen = gen_aarch64_atomic_fetch_anddi_lse;
  else
    gen = gen_aarch64_atomic_fetch_anddi;

  emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit (operand1, true);
  emit_insn (gen_rtx_AND (DImode,
	operand2,
	operand3));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_127 (rtx_insn *, rtx *);
rtx_insn *
gen_split_127 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_127\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_128 (rtx_insn *, rtx *);
rtx_insn *
gen_split_128 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_128\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_129 (rtx_insn *, rtx *);
rtx_insn *
gen_split_129 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_129\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_130 (rtx_insn *, rtx *);
rtx_insn *
gen_split_130 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_130\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_131 (rtx_insn *, rtx *);
rtx_insn *
gen_split_131 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_131\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_132 (rtx_insn *, rtx *);
rtx_insn *
gen_split_132 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_132\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_133 (rtx_insn *, rtx *);
rtx_insn *
gen_split_133 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_133\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_134 (rtx_insn *, rtx *);
rtx_insn *
gen_split_134 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_134\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_135 (rtx_insn *, rtx *);
rtx_insn *
gen_split_135 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_135\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_136 (rtx_insn *, rtx *);
rtx_insn *
gen_split_136 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_136\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_137 (rtx_insn *, rtx *);
rtx_insn *
gen_split_137 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_137\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_138 (rtx_insn *, rtx *);
rtx_insn *
gen_split_138 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_138\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_139 (rtx_insn *, rtx *);
rtx_insn *
gen_split_139 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_139\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_140 (rtx_insn *, rtx *);
rtx_insn *
gen_split_140 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_140\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_141 (rtx_insn *, rtx *);
rtx_insn *
gen_split_141 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_141\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_142 (rtx_insn *, rtx *);
rtx_insn *
gen_split_142 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_142\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_143 (rtx_insn *, rtx *);
rtx_insn *
gen_split_143 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_143\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_144 (rtx_insn *, rtx *);
rtx_insn *
gen_split_144 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_144\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_145 (rtx_insn *, rtx *);
rtx_insn *
gen_split_145 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_145\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:306 */
extern rtx_insn *gen_split_146 (rtx_insn *, rtx *);
rtx_insn *
gen_split_146 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_146\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 322 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, operands[0], operands[4], operands[1],
			     operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_147 (rtx_insn *, rtx *);
rtx_insn *
gen_split_147 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_147\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_148 (rtx_insn *, rtx *);
rtx_insn *
gen_split_148 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_148\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_149 (rtx_insn *, rtx *);
rtx_insn *
gen_split_149 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_149\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_150 (rtx_insn *, rtx *);
rtx_insn *
gen_split_150 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_150\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_151 (rtx_insn *, rtx *);
rtx_insn *
gen_split_151 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_151\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_152 (rtx_insn *, rtx *);
rtx_insn *
gen_split_152 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_152\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_153 (rtx_insn *, rtx *);
rtx_insn *
gen_split_153 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_153\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_154 (rtx_insn *, rtx *);
rtx_insn *
gen_split_154 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_154\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_155 (rtx_insn *, rtx *);
rtx_insn *
gen_split_155 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_155\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_156 (rtx_insn *, rtx *);
rtx_insn *
gen_split_156 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_156\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_157 (rtx_insn *, rtx *);
rtx_insn *
gen_split_157 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_157\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_158 (rtx_insn *, rtx *);
rtx_insn *
gen_split_158 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_158\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_159 (rtx_insn *, rtx *);
rtx_insn *
gen_split_159 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_159\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_160 (rtx_insn *, rtx *);
rtx_insn *
gen_split_160 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_160\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_161 (rtx_insn *, rtx *);
rtx_insn *
gen_split_161 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_161\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_162 (rtx_insn *, rtx *);
rtx_insn *
gen_split_162 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_162\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_163 (rtx_insn *, rtx *);
rtx_insn *
gen_split_163 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_163\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_164 (rtx_insn *, rtx *);
rtx_insn *
gen_split_164 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_164\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_165 (rtx_insn *, rtx *);
rtx_insn *
gen_split_165 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_165\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:329 */
extern rtx_insn *gen_split_166 (rtx_insn *, rtx *);
rtx_insn *
gen_split_166 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_166\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 342 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[0], NULL, operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:349 */
extern rtx_insn *gen_split_167 (rtx_insn *, rtx *);
rtx_insn *
gen_split_167 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_167\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 366 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
			    operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:349 */
extern rtx_insn *gen_split_168 (rtx_insn *, rtx *);
rtx_insn *
gen_split_168 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_168\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 366 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
			    operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:349 */
extern rtx_insn *gen_split_169 (rtx_insn *, rtx *);
rtx_insn *
gen_split_169 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_169\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 366 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
			    operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:349 */
extern rtx_insn *gen_split_170 (rtx_insn *, rtx *);
rtx_insn *
gen_split_170 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_170\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 366 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, operands[0], operands[4], operands[1],
			    operands[2], operands[3], operands[5]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_add_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (PLUS))
    gen = gen_aarch64_atomic_add_fetchqi_lse;
  else
    gen = gen_aarch64_atomic_add_fetchqi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_sub_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (MINUS))
    gen = gen_aarch64_atomic_sub_fetchqi_lse;
  else
    gen = gen_aarch64_atomic_sub_fetchqi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_or_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (IOR))
    gen = gen_aarch64_atomic_or_fetchqi_lse;
  else
    gen = gen_aarch64_atomic_or_fetchqi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_xor_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (XOR))
    gen = gen_aarch64_atomic_xor_fetchqi_lse;
  else
    gen = gen_aarch64_atomic_xor_fetchqi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_and_fetchqi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (AND))
    gen = gen_aarch64_atomic_and_fetchqi_lse;
  else
    gen = gen_aarch64_atomic_and_fetchqi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (QImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_add_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (PLUS))
    gen = gen_aarch64_atomic_add_fetchhi_lse;
  else
    gen = gen_aarch64_atomic_add_fetchhi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_sub_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (MINUS))
    gen = gen_aarch64_atomic_sub_fetchhi_lse;
  else
    gen = gen_aarch64_atomic_sub_fetchhi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_or_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (IOR))
    gen = gen_aarch64_atomic_or_fetchhi_lse;
  else
    gen = gen_aarch64_atomic_or_fetchhi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_xor_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (XOR))
    gen = gen_aarch64_atomic_xor_fetchhi_lse;
  else
    gen = gen_aarch64_atomic_xor_fetchhi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_and_fetchhi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (AND))
    gen = gen_aarch64_atomic_and_fetchhi_lse;
  else
    gen = gen_aarch64_atomic_and_fetchhi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (HImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_add_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (PLUS))
    gen = gen_aarch64_atomic_add_fetchsi_lse;
  else
    gen = gen_aarch64_atomic_add_fetchsi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_sub_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (MINUS))
    gen = gen_aarch64_atomic_sub_fetchsi_lse;
  else
    gen = gen_aarch64_atomic_sub_fetchsi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_or_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (IOR))
    gen = gen_aarch64_atomic_or_fetchsi_lse;
  else
    gen = gen_aarch64_atomic_or_fetchsi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_xor_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (XOR))
    gen = gen_aarch64_atomic_xor_fetchsi_lse;
  else
    gen = gen_aarch64_atomic_xor_fetchsi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_and_fetchsi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (AND))
    gen = gen_aarch64_atomic_and_fetchsi_lse;
  else
    gen = gen_aarch64_atomic_and_fetchsi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (SImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_add_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (PLUS))
    gen = gen_aarch64_atomic_add_fetchdi_lse;
  else
    gen = gen_aarch64_atomic_add_fetchdi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_PLUS (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_sub_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (MINUS))
    gen = gen_aarch64_atomic_sub_fetchdi_lse;
  else
    gen = gen_aarch64_atomic_sub_fetchdi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_MINUS (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_or_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (IOR))
    gen = gen_aarch64_atomic_or_fetchdi_lse;
  else
    gen = gen_aarch64_atomic_or_fetchdi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_IOR (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_xor_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (XOR))
    gen = gen_aarch64_atomic_xor_fetchdi_lse;
  else
    gen = gen_aarch64_atomic_xor_fetchdi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_XOR (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:375 */
rtx
gen_atomic_and_fetchdi (rtx operand0,
	rtx operand1,
	rtx operand2,
	rtx operand3)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[4];
    operands[0] = operand0;
    operands[1] = operand1;
    operands[2] = operand2;
    operands[3] = operand3;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 382 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
  rtx (*gen) (rtx, rtx, rtx, rtx);
  rtx value = operands[2];

  /* Use an atomic load-operate instruction when possible.  */
  if (aarch64_atomic_ldop_supported_p (AND))
    gen = gen_aarch64_atomic_and_fetchdi_lse;
  else
    gen = gen_aarch64_atomic_and_fetchdi;

  emit_insn (gen (operands[0], operands[1], value, operands[3]));

  DONE;
}
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
    operand2 = operands[2];
    (void) operand2;
    operand3 = operands[3];
    (void) operand3;
  }
  emit (operand0, true);
  emit_insn (gen_rtx_AND (DImode,
	operand1,
	operand2));
  emit (operand3, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_171 (rtx_insn *, rtx *);
rtx_insn *
gen_split_171 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_171\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_172 (rtx_insn *, rtx *);
rtx_insn *
gen_split_172 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_172\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_173 (rtx_insn *, rtx *);
rtx_insn *
gen_split_173 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_173\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_174 (rtx_insn *, rtx *);
rtx_insn *
gen_split_174 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_174\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_175 (rtx_insn *, rtx *);
rtx_insn *
gen_split_175 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_175\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_176 (rtx_insn *, rtx *);
rtx_insn *
gen_split_176 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_176\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_177 (rtx_insn *, rtx *);
rtx_insn *
gen_split_177 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_177\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_178 (rtx_insn *, rtx *);
rtx_insn *
gen_split_178 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_178\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_179 (rtx_insn *, rtx *);
rtx_insn *
gen_split_179 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_179\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_180 (rtx_insn *, rtx *);
rtx_insn *
gen_split_180 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_180\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_181 (rtx_insn *, rtx *);
rtx_insn *
gen_split_181 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_181\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_182 (rtx_insn *, rtx *);
rtx_insn *
gen_split_182 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_182\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_183 (rtx_insn *, rtx *);
rtx_insn *
gen_split_183 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_183\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_184 (rtx_insn *, rtx *);
rtx_insn *
gen_split_184 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_184\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_185 (rtx_insn *, rtx *);
rtx_insn *
gen_split_185 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_185\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_186 (rtx_insn *, rtx *);
rtx_insn *
gen_split_186 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_186\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (PLUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_187 (rtx_insn *, rtx *);
rtx_insn *
gen_split_187 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_187\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (MINUS, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_188 (rtx_insn *, rtx *);
rtx_insn *
gen_split_188 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_188\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (IOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_189 (rtx_insn *, rtx *);
rtx_insn *
gen_split_189 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_189\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (XOR, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:397 */
extern rtx_insn *gen_split_190 (rtx_insn *, rtx *);
rtx_insn *
gen_split_190 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_190\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 413 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (AND, NULL, operands[0], operands[1],
			     operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_191 (rtx_insn *, rtx *);
rtx_insn *
gen_split_191 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_191\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_192 (rtx_insn *, rtx *);
rtx_insn *
gen_split_192 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_192\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_193 (rtx_insn *, rtx *);
rtx_insn *
gen_split_193 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_193\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_194 (rtx_insn *, rtx *);
rtx_insn *
gen_split_194 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_194\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_195 (rtx_insn *, rtx *);
rtx_insn *
gen_split_195 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_195\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_196 (rtx_insn *, rtx *);
rtx_insn *
gen_split_196 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_196\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_197 (rtx_insn *, rtx *);
rtx_insn *
gen_split_197 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_197\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_198 (rtx_insn *, rtx *);
rtx_insn *
gen_split_198 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_198\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_199 (rtx_insn *, rtx *);
rtx_insn *
gen_split_199 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_199\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_200 (rtx_insn *, rtx *);
rtx_insn *
gen_split_200 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_200\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_201 (rtx_insn *, rtx *);
rtx_insn *
gen_split_201 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_201\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_202 (rtx_insn *, rtx *);
rtx_insn *
gen_split_202 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_202\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_203 (rtx_insn *, rtx *);
rtx_insn *
gen_split_203 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_203\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_204 (rtx_insn *, rtx *);
rtx_insn *
gen_split_204 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_204\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_205 (rtx_insn *, rtx *);
rtx_insn *
gen_split_205 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_205\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_206 (rtx_insn *, rtx *);
rtx_insn *
gen_split_206 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_206\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (PLUS, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_207 (rtx_insn *, rtx *);
rtx_insn *
gen_split_207 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_207\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (MINUS, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_208 (rtx_insn *, rtx *);
rtx_insn *
gen_split_208 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_208\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (IOR, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_209 (rtx_insn *, rtx *);
rtx_insn *
gen_split_209 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_209\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (XOR, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:420 */
extern rtx_insn *gen_split_210 (rtx_insn *, rtx *);
rtx_insn *
gen_split_210 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_210\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 436 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_gen_atomic_ldop (AND, operands[4], operands[0], operands[1],
			     operands[2], operands[3]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:443 */
extern rtx_insn *gen_split_211 (rtx_insn *, rtx *);
rtx_insn *
gen_split_211 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_211\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 460 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
			    operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:443 */
extern rtx_insn *gen_split_212 (rtx_insn *, rtx *);
rtx_insn *
gen_split_212 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_212\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 460 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
			    operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:443 */
extern rtx_insn *gen_split_213 (rtx_insn *, rtx *);
rtx_insn *
gen_split_213 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_213\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 460 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
			    operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:443 */
extern rtx_insn *gen_split_214 (rtx_insn *, rtx *);
rtx_insn *
gen_split_214 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_split_214\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 460 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    aarch64_split_atomic_op (NOT, NULL, operands[0], operands[1],
			    operands[2], operands[3], operands[4]);
    DONE;
  }
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:550 */
rtx
gen_mem_thread_fence (rtx operand0)
{
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[1];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 553 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    enum memmodel model = memmodel_from_int (INTVAL (operands[0]));
    if (!(is_mm_relaxed (model) || is_mm_consume (model)))
      emit_insn (gen_dmb (operands[0]));
    DONE;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
  }
  emit (operand0, false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md:561 */
rtx
gen_dmb (rtx operand0)
{
  rtx operand1;
  rtx_insn *_val = 0;
  start_sequence ();
  {
    rtx operands[2];
    operands[0] = operand0;
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 566 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/atomics.md"
{
    operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
    MEM_VOLATILE_P (operands[1]) = 1;
  }
#undef DONE
#undef FAIL
    operand0 = operands[0];
    (void) operand0;
    operand1 = operands[1];
    (void) operand1;
  }
  emit_insn (gen_rtx_SET (operand1,
	gen_rtx_UNSPEC (BLKmode,
	gen_rtvec (2,
		copy_rtx (operand1),
		operand0),
	37)));
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:21 */
extern rtx_insn *gen_peephole2_4 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_4 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_4\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 29 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:21 */
extern rtx_insn *gen_peephole2_5 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_5 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_5\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 29 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:41 */
extern rtx_insn *gen_peephole2_6 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_6 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_6\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 49 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:41 */
extern rtx_insn *gen_peephole2_7 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_7 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_7\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 49 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:61 */
extern rtx_insn *gen_peephole2_8 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_8 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_8\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:61 */
extern rtx_insn *gen_peephole2_9 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_9 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_9\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 69 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_10 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_10 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_10\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 89 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:81 */
extern rtx_insn *gen_peephole2_11 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_11 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_11\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 89 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:101 */
extern rtx_insn *gen_peephole2_12 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_12 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_12\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 109 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:101 */
extern rtx_insn *gen_peephole2_13 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_13 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_13\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 109 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:101 */
extern rtx_insn *gen_peephole2_14 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_14 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_14\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 109 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:101 */
extern rtx_insn *gen_peephole2_15 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_15 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_15\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 109 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:101 */
extern rtx_insn *gen_peephole2_16 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_16 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_16\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 109 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:121 */
extern rtx_insn *gen_peephole2_17 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_17 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_17\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 129 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:121 */
extern rtx_insn *gen_peephole2_18 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_18 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_18\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 129 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:121 */
extern rtx_insn *gen_peephole2_19 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_19 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_19\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 129 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:121 */
extern rtx_insn *gen_peephole2_20 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_20 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_20\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 129 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:121 */
extern rtx_insn *gen_peephole2_21 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_21 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_21\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 129 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	operand1),
		gen_rtx_SET (operand2,
	operand3))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:144 */
extern rtx_insn *gen_peephole2_22 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_22 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_22\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 152 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_SIGN_EXTEND (DImode,
	operand1)),
		gen_rtx_SET (operand2,
	gen_rtx_SIGN_EXTEND (DImode,
	operand3)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:164 */
extern rtx_insn *gen_peephole2_23 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_23 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands)
{
  rtx operand0;
  rtx operand1;
  rtx operand2;
  rtx operand3;
  rtx_insn *_val = NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_23\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 172 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[2]);
      std::swap (operands[1], operands[3]);
    }
}
#undef DONE
#undef FAIL
  operand0 = operands[0];
  (void) operand0;
  operand1 = operands[1];
  (void) operand1;
  operand2 = operands[2];
  (void) operand2;
  operand3 = operands[3];
  (void) operand3;
  emit (gen_rtx_PARALLEL (VOIDmode,
	gen_rtvec (2,
		gen_rtx_SET (operand0,
	gen_rtx_ZERO_EXTEND (DImode,
	operand1)),
		gen_rtx_SET (operand2,
	gen_rtx_ZERO_EXTEND (DImode,
	operand3)))), false);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:189 */
extern rtx_insn *gen_peephole2_24 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_24 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_24\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 202 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:189 */
extern rtx_insn *gen_peephole2_25 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_25 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_25\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 202 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, true, DImode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:221 */
extern rtx_insn *gen_peephole2_26 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_26 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_26\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 234 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, true, SFmode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:221 */
extern rtx_insn *gen_peephole2_27 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_27 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_27\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 234 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, true, DFmode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:253 */
extern rtx_insn *gen_peephole2_28 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_28 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_28\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 266 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, SIGN_EXTEND))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:285 */
extern rtx_insn *gen_peephole2_29 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_29 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_29\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 298 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[1], &base, &offset_1);
  extract_base_offset_in_addr (operands[3], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, true, SImode, ZERO_EXTEND))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:317 */
extern rtx_insn *gen_peephole2_30 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_30 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_30\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 330 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, false, SImode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:317 */
extern rtx_insn *gen_peephole2_31 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_31 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_31\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 330 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, false, DImode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:349 */
extern rtx_insn *gen_peephole2_32 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_32 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_32\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 362 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, false, SFmode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}

/* ../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md:349 */
extern rtx_insn *gen_peephole2_33 (rtx_insn *, rtx *);
rtx_insn *
gen_peephole2_33 (rtx_insn *curr_insn ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
{
  rtx_insn *_val = NULL;
  HARD_REG_SET _regs_allocated;
  CLEAR_HARD_REG_SET (_regs_allocated);
  if ((operands[8] = peep2_find_free_register (0, 4, "r", DImode, &_regs_allocated)) == NULL_RTX)
    return NULL;
  if (dump_file)
    fprintf (dump_file, "Splitting with gen_peephole2_33\n");
  start_sequence ();
#define FAIL return (end_sequence (), _val)
#define DONE return (_val = get_insns (),end_sequence (), _val)
#line 362 "../../../../../../../work-shared/gcc-linaro-6.2-r2016.11/git/gcc/config/aarch64/aarch64-ldpstp.md"
{
  rtx base, offset_1, offset_2;

  extract_base_offset_in_addr (operands[0], &base, &offset_1);
  extract_base_offset_in_addr (operands[2], &base, &offset_2);
  if (INTVAL (offset_1) > INTVAL (offset_2))
    {
      std::swap (operands[0], operands[6]);
      std::swap (operands[1], operands[7]);
      std::swap (operands[2], operands[4]);
      std::swap (operands[3], operands[5]);
    }

  if (aarch64_gen_adjusted_ldpstp (operands, false, DFmode, UNKNOWN))
    DONE;
  else
    FAIL;
}
#undef DONE
#undef FAIL
  emit_insn (const0_rtx);
  _val = get_insns ();
  end_sequence ();
  return _val;
}



void
add_clobbers (rtx pattern ATTRIBUTE_UNUSED, int insn_code_number)
{
  switch (insn_code_number)
    {
    case 3245:
    case 3244:
    case 3243:
    case 3242:
    case 3241:
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    case 3240:
    case 3239:
    case 3238:
    case 3237:
    case 3236:
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3235:
    case 3234:
    case 3233:
    case 3232:
    case 3231:
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode));
      break;

    case 3230:
    case 3229:
    case 3228:
    case 3227:
    case 3226:
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode));
      break;

    case 3205:
    case 3181:
    case 3180:
    case 3179:
    case 3178:
    case 3177:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3204:
    case 3176:
    case 3175:
    case 3174:
    case 3173:
    case 3172:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3203:
    case 3171:
    case 3170:
    case 3169:
    case 3168:
    case 3167:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode));
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3202:
    case 3166:
    case 3165:
    case 3164:
    case 3163:
    case 3162:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode));
      XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3147:
    case 3146:
    case 3145:
    case 3144:
    case 3143:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode));
      break;

    case 3142:
    case 3141:
    case 3140:
    case 3139:
    case 3138:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode));
      break;

    case 3161:
    case 3137:
    case 3136:
    case 3135:
    case 3134:
    case 3133:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3160:
    case 3132:
    case 3131:
    case 3130:
    case 3129:
    case 3128:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3159:
    case 3127:
    case 3126:
    case 3125:
    case 3124:
    case 3123:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (HImode));
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3158:
    case 3122:
    case 3121:
    case 3120:
    case 3119:
    case 3118:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (QImode));
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3249:
    case 3248:
    case 3247:
    case 3246:
    case 3225:
    case 3224:
    case 3223:
    case 3222:
    case 3221:
    case 3220:
    case 3219:
    case 3218:
    case 3217:
    case 3216:
    case 3215:
    case 3214:
    case 3213:
    case 3212:
    case 3211:
    case 3210:
    case 3209:
    case 3208:
    case 3207:
    case 3206:
    case 3113:
    case 3112:
    case 3111:
    case 3110:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3105:
    case 3104:
    case 3103:
    case 3102:
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 3157:
    case 3156:
    case 3155:
    case 3154:
    case 3153:
    case 961:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    case 3152:
    case 3151:
    case 3150:
    case 3149:
    case 3148:
    case 960:
      XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (SImode));
      break;

    case 953:
    case 952:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (DImode, 30);
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (CCmode, 66);
      XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
	gen_rtx_SCRATCH (DImode));
      break;

    case 937:
    case 44:
    case 43:
    case 42:
    case 41:
      XVECEXP (pattern, 0, 2) = gen_hard_reg_clobber (DImode, 30);
      break;

    case 2568:
    case 2556:
    case 2555:
    case 2554:
    case 2553:
    case 2519:
    case 2518:
    case 2517:
    case 2516:
    case 2515:
    case 40:
    case 39:
    case 38:
    case 37:
    case 36:
    case 35:
    case 34:
    case 33:
    case 32:
    case 31:
    case 30:
    case 29:
      XVECEXP (pattern, 0, 1) = gen_hard_reg_clobber (CCmode, 66);
      break;

    default:
      gcc_unreachable ();
    }
}


int
added_clobbers_hard_reg_p (int insn_code_number)
{
  switch (insn_code_number)
    {
    case 3245:
    case 3244:
    case 3243:
    case 3242:
    case 3241:
    case 3240:
    case 3239:
    case 3238:
    case 3237:
    case 3236:
    case 3235:
    case 3234:
    case 3233:
    case 3232:
    case 3231:
    case 3230:
    case 3229:
    case 3228:
    case 3227:
    case 3226:
    case 3147:
    case 3146:
    case 3145:
    case 3144:
    case 3143:
    case 3142:
    case 3141:
    case 3140:
    case 3139:
    case 3138:
    case 3105:
    case 3104:
    case 3103:
    case 3102:
    case 3157:
    case 3156:
    case 3155:
    case 3154:
    case 3153:
    case 961:
    case 3152:
    case 3151:
    case 3150:
    case 3149:
    case 3148:
    case 960:
      return 0;

    case 3205:
    case 3181:
    case 3180:
    case 3179:
    case 3178:
    case 3177:
    case 3204:
    case 3176:
    case 3175:
    case 3174:
    case 3173:
    case 3172:
    case 3203:
    case 3171:
    case 3170:
    case 3169:
    case 3168:
    case 3167:
    case 3202:
    case 3166:
    case 3165:
    case 3164:
    case 3163:
    case 3162:
    case 3161:
    case 3137:
    case 3136:
    case 3135:
    case 3134:
    case 3133:
    case 3160:
    case 3132:
    case 3131:
    case 3130:
    case 3129:
    case 3128:
    case 3159:
    case 3127:
    case 3126:
    case 3125:
    case 3124:
    case 3123:
    case 3158:
    case 3122:
    case 3121:
    case 3120:
    case 3119:
    case 3118:
    case 3249:
    case 3248:
    case 3247:
    case 3246:
    case 3225:
    case 3224:
    case 3223:
    case 3222:
    case 3221:
    case 3220:
    case 3219:
    case 3218:
    case 3217:
    case 3216:
    case 3215:
    case 3214:
    case 3213:
    case 3212:
    case 3211:
    case 3210:
    case 3209:
    case 3208:
    case 3207:
    case 3206:
    case 3113:
    case 3112:
    case 3111:
    case 3110:
    case 953:
    case 952:
    case 937:
    case 44:
    case 43:
    case 42:
    case 41:
    case 2568:
    case 2556:
    case 2555:
    case 2554:
    case 2553:
    case 2519:
    case 2518:
    case 2517:
    case 2516:
    case 2515:
    case 40:
    case 39:
    case 38:
    case 37:
    case 36:
    case 35:
    case 34:
    case 33:
    case 32:
    case 31:
    case 30:
    case 29:
      return 1;

    default:
      gcc_unreachable ();
    }
}
