Zynq UltraScale+ MPSoC PS configuration detail

Zynq UltraScale+ Summary Report
User Configurations
MIO Configurations

CLK Configurations

DDR Configurations

GT Configurations
This design is targeted for xck24 board (part number: xck24-ubva530-2lv-c)

## Zynq UltraScale+ Design Summary

Device | xck24
SpeedGrade | -2lv
Part | xck24-ubva530-2lv-c
Description | Zynq UltraScale+ PS Configuration Report
Vendor | Xilinx

## MIO Table View

MIO Pin | Peripheral | Signal | IO Type | Speed | Pullup | Direction | Drive Strength(mA)
MIO 0 | Quad SPI Flash | sclk_out | cmos | slow | pullup | out | 4
MIO 1 | Quad SPI Flash | miso_mo1 | cmos | slow | pullup | inout | 4
MIO 2 | Quad SPI Flash | mo2 | cmos | slow | pullup | inout | 4
MIO 3 | Quad SPI Flash | mo3 | cmos | slow | pullup | inout | 4
MIO 4 | Quad SPI Flash | mosi_mi0 | cmos | slow | pullup | inout | 4
MIO 5 | Quad SPI Flash | n_ss_out | cmos | slow | pullup | out | 4
MIO 6 | SPI 1 | sclk_out | cmos | slow | pullup | inout | 4
MIO 7 | GPIO0 MIO | gpio0[7] | cmos | slow | pullup | inout | 4
MIO 8 | GPIO0 MIO | gpio0[8] | cmos | slow | pullup | inout | 4
MIO 9 | SPI 1 | n_ss_out[0] | cmos | slow | pullup | inout | 4
MIO 10 | SPI 1 | miso | cmos | slow | pullup | inout | 4
MIO 11 | SPI 1 | mosi | cmos | slow | pullup | inout | 4
MIO 12 | GPIO0 MIO | gpio0[12] | cmos | slow | pullup | inout | 4
MIO 13 | SD 0 | sdio0_data_out[0] | cmos | slow | pullup | inout | 4
MIO 14 | SD 0 | sdio0_data_out[1] | cmos | slow | pullup | inout | 4
MIO 15 | SD 0 | sdio0_data_out[2] | cmos | slow | pullup | inout | 4
MIO 16 | SD 0 | sdio0_data_out[3] | cmos | slow | pullup | inout | 4
MIO 17 | SD 0 | sdio0_data_out[4] | cmos | slow | pullup | inout | 4
MIO 18 | SD 0 | sdio0_data_out[5] | cmos | slow | pullup | inout | 4
MIO 19 | SD 0 | sdio0_data_out[6] | cmos | slow | pullup | inout | 4
MIO 20 | SD 0 | sdio0_data_out[7] | cmos | slow | pullup | inout | 4
MIO 21 | SD 0 | sdio0_cmd_out | cmos | slow | pullup | inout | 4
MIO 22 | SD 0 | sdio0_clk_out | cmos | slow | pullup | out | 4
MIO 23 | SD 0 | sdio0_bus_pow | cmos | slow | pullup | out | 4
MIO 24 | I2C 1 | scl_out | cmos | slow | pullup | inout | 4
MIO 25 | I2C 1 | sda_out | cmos | slow | pullup | inout | 4
MIO 26 | GPIO1 MIO | gpio1[26] | cmos | slow | pullup | inout | 4
MIO 27 | GPIO1 MIO | gpio1[27] | cmos | slow | pullup | inout | 4
MIO 28 | GPIO1 MIO | gpio1[28] | cmos | fast | pullup | inout | 12
MIO 29 | GPIO1 MIO | gpio1[29] | cmos | slow | pullup | inout | 4
MIO 30 | GPIO1 MIO | gpio1[30] | cmos | fast | pullup | inout | 12
MIO 31 | GPIO1 MIO | gpio1[31] | cmos | slow | pullup | inout | 4
MIO 32 | PMU GPO 0 | gpo[0] | cmos | slow | pullup | out | 4
MIO 33 | PMU GPO 1 | gpo[1] | cmos | slow | pullup | out | 4
MIO 34 | GPIO1 MIO | gpio1[34] | cmos | slow | pullup | inout | 4
MIO 35 | GPIO1 MIO | gpio1[35] | cmos | slow | pullup | inout | 4
MIO 36 | UART 1 | txd | cmos | slow | pullup | out | 4
MIO 37 | UART 1 | rxd | cmos | fast | pullup | in | 12
MIO 38 | GPIO1 MIO | gpio1[38] | cmos | slow | pullup | inout | 4
MIO 39 | GPIO1 MIO | gpio1[39] | cmos | slow | pullup | inout | 4
MIO 40 | GPIO1 MIO | gpio1[40] | cmos | slow | pullup | inout | 4
MIO 41 | GPIO1 MIO | gpio1[41] | cmos | slow | pullup | inout | 4
MIO 42 | GPIO1 MIO | gpio1[42] | cmos | slow | pullup | inout | 4
MIO 43 | GPIO1 MIO | gpio1[43] | cmos | slow | pullup | inout | 4
MIO 44 | GPIO1 MIO | gpio1[44] | cmos | slow | pullup | inout | 4
MIO 45 | GPIO1 MIO | gpio1[45] | cmos | fast | pullup | inout | 12
MIO 46 | GPIO1 MIO | gpio1[46] | cmos | slow | pullup | inout | 4
MIO 47 | TTC 0 | wave_out | cmos | slow | pullup | out | 4
MIO 48 | GPIO1 MIO | gpio1[48] | cmos | slow | pullup | inout | 4
MIO 49 | GPIO1 MIO | gpio1[49] | cmos | slow | pullup | inout | 4
MIO 50 | MDIO 1 | gem1_mdc | cmos | slow | pullup | out | 4
MIO 51 | MDIO 1 | gem1_mdio_out | cmos | slow | pullup | inout | 4
MIO 52 | USB 0 | ulpi_clk_in | cmos | fast | pullup | in | 12
MIO 53 | USB 0 | ulpi_dir | cmos | fast | pullup | in | 12
MIO 54 | USB 0 | ulpi_tx_data[2] | cmos | slow | pullup | inout | 4
MIO 55 | USB 0 | ulpi_nxt | cmos | fast | pullup | in | 12
MIO 56 | USB 0 | ulpi_tx_data[0] | cmos | slow | pullup | inout | 4
MIO 57 | USB 0 | ulpi_tx_data[1] | cmos | slow | pullup | inout | 4
MIO 58 | USB 0 | ulpi_stp | cmos | slow | pullup | out | 4
MIO 59 | USB 0 | ulpi_tx_data[3] | cmos | slow | pullup | inout | 4
MIO 60 | USB 0 | ulpi_tx_data[4] | cmos | slow | pullup | inout | 4
MIO 61 | USB 0 | ulpi_tx_data[5] | cmos | slow | pullup | inout | 4
MIO 62 | USB 0 | ulpi_tx_data[6] | cmos | slow | pullup | inout | 4
MIO 63 | USB 0 | ulpi_tx_data[7] | cmos | slow | pullup | inout | 4
MIO 64 | GPIO2 MIO | gpio2[64] | cmos | slow | pullup | inout | 4
MIO 65 | GPIO2 MIO | gpio2[65] | cmos | slow | pullup | inout | 4
MIO 66 | I2C 0 | scl_out | cmos | slow | pullup | inout | 4
MIO 67 | I2C 0 | sda_out | cmos | slow | pullup | inout | 4
MIO 68 | GPIO2 MIO | gpio2[68] | cmos | slow | pullup | inout | 4
MIO 69 | GPIO2 MIO | gpio2[69] | cmos | slow | pullup | inout | 4
MIO 70 | UART 0 | rxd | cmos | fast | pullup | in | 12
MIO 71 | UART 0 | txd | cmos | slow | pullup | out | 4
MIO 72 | GPIO2 MIO | gpio2[72] | cmos | slow | pullup | inout | 4
MIO 73 | GPIO2 MIO | gpio2[73] | cmos | slow | pullup | inout | 4
MIO 74 | GPIO2 MIO | gpio2[74] | cmos | slow | pullup | inout | 4
MIO 75 | GPIO2 MIO | gpio2[75] | cmos | slow | pullup | inout | 4
MIO 76 | GPIO2 MIO | gpio2[76] | cmos | slow | pullup | inout | 4
MIO 77 | GPIO2 MIO | gpio2[77] | cmos | slow | pullup | inout | 4

## PS Clocks information

PSS REF CLK : 33.333

Name | Source | Input Frequency (MHz)
APLL | PSS_REF_CLK | 2633.307
DPLL | PSS_REF_CLK | 2099.979
VPLL | PSS_REF_CLK | 2999.970
RPLL | PSS_REF_CLK | 2133.312
IOPLL | PSS_REF_CLK | 2999.970

Peripheral | Requested Frequency (MHz) | Source | Actual Frequency (MHz)
GEM1 freq (MHz) | 125 | IOPLL | 124.998749
USB0 freq (MHz) | 250 | IOPLL | 249.997498
QSPI freq (MHz) | 125 | IOPLL | 124.998749
SDIO0 freq (MHz) | 200 | IOPLL | 187.498123
UART0 freq (MHz) | 100 | IOPLL | 99.999001
UART1 freq (MHz) | 100 | IOPLL | 99.999001
I2C0 freq (MHz) | 100 | IOPLL | 99.999001
I2C1 freq (MHz) | 100 | IOPLL | 99.999001
SPI1 freq (MHz) | 200 | IOPLL | 187.498123
CPU_R5 freq (MHz) | 533.333 | RPLL | 533.328003
IOU_SWITCH freq (MHz) | 250 | IOPLL | 249.997498
LPD_SWITCH freq (MHz) | 500 | IOPLL | 499.994995
LPD_LSBUS freq (MHz) | 100 | IOPLL | 99.999001
GEM_TSU freq (MHz) | 250 | IOPLL | 249.997498
TIMESTAMP freq (MHz) | 100 | IOPLL | 99.999001
PSU__CRL_APB__USB3_REF_CTRL__freqmhz | 20 | IOPLL | 19.999800
PCAP freq (MHz) | 200 | IOPLL | 187.498123
DBG_LPD freq (MHz) | 250 | IOPLL | 249.997498
ADMA freq (MHz) | 500 | IOPLL | 499.994995
PL0 freq (MHz) | 100 | IOPLL | 99.999001
AMS freq (MHz) | 50 | IOPLL | 49.999500
ACPU freq (MHz) | 1333 | APLL | 1333.000000
DBG FPD freq (MHz) | 250 | IOPLL | 249.997498
DDR_CTRL freq MHz) | 266.500 | DPLL | 262.497375
GPU freq (MHz) | 600 | DPLL | 524.994751
GDMA freq (MHz) | 600 | DPLL | 524.994751
DPDMA freq (MHz) | 600 | APLL | 444.333344
TOPSW_MAIN freq (MHz) | 533.33 | DPLL | 524.994751
TOPSW_LSBUS freq (MHz) | 100 | IOPLL | 99.999001
DBG TSTMP freq (MHz) | 250 | IOPLL | 249.997498

## DDR Memory information

Parameter name | Value | Description
ENABLE | 1 | Enable the PS DDR Controller
DDR Interface freq (MHz) | 533 | --
MEMORY TYPE | LPDDR 4 | Type of memory interface
DM DBI | Components |
BUS WIDTH | 32 Bit | Data width of DDR interface, not including ECC data width
ECC | Disabled | Enables error correction code support
SPEED BIN | LPDDR4_1066 | Speed Bin
CL | NA | Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL | NA | CAS write latency setting in memory clock cycles
DDR AL | 0 | Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD | 10 | tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP | 12 | Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC | 63 | Row cycle time (ns)
T RAS MIN | 42 | Minimum number of memory clock cycles required between an Active and Precharge command
T FAW | 40.0 | Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH | 32 Bits | Width of individual DRAM components
DEVICE CAPACITY | 16384 MBits | Storage capacity of individual DRAM components
BG ADDR COUNT | NA | Number of bank group address pins
RANK ADDR COUNT | 0 | Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT | 3 | Number of bank address pins
ROW ADDR COUNT | 16 | Number of row address pins
COL ADDR COUNT | 10 | Number of column address bits
C_DDR_RAM_HIGHADDR | 0x7FFFFFFF | --

## GT lanes information

Protocol | GT lane# | Ref Clk Sel | Ref freq (MHz)
Gem1 | GT Lane1 | Ref Clk1 | 125
USB0 | GT Lane2 | Ref Clk2 | 26