/* SPDX-License-Identifier: GPL-2.0 */
/*
 *  Copyright (C) 2022 Xilinx-2022 Xilinx, Inc.
 * (C) Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
 */

#ifndef _DT_BINDINGS_VERSAL_REGNODE_H
#define _DT_BINDINGS_VERSAL_REGNODE_H

#define PM_REGNODE_SYSMON_ROOT_0			(0x18224055U)
#define PM_REGNODE_SYSMON_ROOT_1			(0x18225055U)
#define PM_REGNODE_SYSMON_ROOT_2			(0x18226055U)
#define PM_REGNODE_SYSMON_ROOT_3			(0x18227055U)

#endif
