#ifndef XPARAMETERS_H   /* prevent circular inclusions */
#define XPARAMETERS_H   /* by using protection macros */

#define XPAR_XCFRAME_NUM_INSTANCES 16

/* Definitions for peripheral PMC_CFI_CFRAME_0 */
#define XPAR_PMC_CFI_CFRAME_0_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_PMC_CFI_CFRAME_0_BASEADDR 0xf12d0000
#define XPAR_PMC_CFI_CFRAME_0_HIGHADDR 0xf12d0fff

/* Canonical definitions for peripheral PMC_CFI_CFRAME_0 */
#define XPAR_XCFRAME_0_BASEADDR 0xf12d0000
#define XPAR_XCFRAME_0_HIGHADDR 0xf12d0fff
#define XPAR_XCFRAME_0_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_1 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_1_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_1_BASEADDR 0xf12d2000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_1_HIGHADDR 0xf12d2fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_1 */
#define XPAR_XCFRAME_1_BASEADDR 0xf12d2000
#define XPAR_XCFRAME_1_HIGHADDR 0xf12d2fff
#define XPAR_XCFRAME_1_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_10 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_10_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_10_BASEADDR 0xf12e4000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_10_HIGHADDR 0xf12e4fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_10 */
#define XPAR_XCFRAME_2_BASEADDR 0xf12e4000
#define XPAR_XCFRAME_2_HIGHADDR 0xf12e4fff
#define XPAR_XCFRAME_2_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_11 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_11_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_11_BASEADDR 0xf12e6000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_11_HIGHADDR 0xf12e6fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_11 */
#define XPAR_XCFRAME_3_BASEADDR 0xf12e6000
#define XPAR_XCFRAME_3_HIGHADDR 0xf12e6fff
#define XPAR_XCFRAME_3_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_12 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_12_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_12_BASEADDR 0xf12e8000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_12_HIGHADDR 0xf12e8fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_12 */
#define XPAR_XCFRAME_4_BASEADDR 0xf12e8000
#define XPAR_XCFRAME_4_HIGHADDR 0xf12e8fff
#define XPAR_XCFRAME_4_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_13 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_13_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_13_BASEADDR 0xf12ea000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_13_HIGHADDR 0xf12eafff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_13 */
#define XPAR_XCFRAME_5_BASEADDR 0xf12ea000
#define XPAR_XCFRAME_5_HIGHADDR 0xf12eafff
#define XPAR_XCFRAME_5_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_14 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_14_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_14_BASEADDR 0xf12ec000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_14_HIGHADDR 0xf12ecfff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_14 */
#define XPAR_XCFRAME_6_BASEADDR 0xf12ec000
#define XPAR_XCFRAME_6_HIGHADDR 0xf12ecfff
#define XPAR_XCFRAME_6_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_2 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_2_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_2_BASEADDR 0xf12d4000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_2_HIGHADDR 0xf12d4fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_2 */
#define XPAR_XCFRAME_7_BASEADDR 0xf12d4000
#define XPAR_XCFRAME_7_HIGHADDR 0xf12d4fff
#define XPAR_XCFRAME_7_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_3 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_3_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_3_BASEADDR 0xf12d6000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_3_HIGHADDR 0xf12d6fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_3 */
#define XPAR_XCFRAME_8_BASEADDR 0xf12d6000
#define XPAR_XCFRAME_8_HIGHADDR 0xf12d6fff
#define XPAR_XCFRAME_8_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_4 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_4_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_4_BASEADDR 0xf12d8000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_4_HIGHADDR 0xf12d8fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_4 */
#define XPAR_XCFRAME_9_BASEADDR 0xf12d8000
#define XPAR_XCFRAME_9_HIGHADDR 0xf12d8fff
#define XPAR_XCFRAME_9_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_5 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_5_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_5_BASEADDR 0xf12da000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_5_HIGHADDR 0xf12dafff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_5 */
#define XPAR_XCFRAME_10_BASEADDR 0xf12da000
#define XPAR_XCFRAME_10_HIGHADDR 0xf12dafff
#define XPAR_XCFRAME_10_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_6 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_6_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_6_BASEADDR 0xf12dc000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_6_HIGHADDR 0xf12dcfff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_6 */
#define XPAR_XCFRAME_11_BASEADDR 0xf12dc000
#define XPAR_XCFRAME_11_HIGHADDR 0xf12dcfff
#define XPAR_XCFRAME_11_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_7 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_7_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_7_BASEADDR 0xf12de000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_7_HIGHADDR 0xf12defff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_7 */
#define XPAR_XCFRAME_12_BASEADDR 0xf12de000
#define XPAR_XCFRAME_12_HIGHADDR 0xf12defff
#define XPAR_XCFRAME_12_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_8 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_8_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_8_BASEADDR 0xf12e0000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_8_HIGHADDR 0xf12e0fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_8 */
#define XPAR_XCFRAME_13_BASEADDR 0xf12e0000
#define XPAR_XCFRAME_13_HIGHADDR 0xf12e0fff
#define XPAR_XCFRAME_13_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_9 */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_9_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_9_BASEADDR 0xf12e2000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_9_HIGHADDR 0xf12e2fff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_9 */
#define XPAR_XCFRAME_14_BASEADDR 0xf12e2000
#define XPAR_XCFRAME_14_HIGHADDR 0xf12e2fff
#define XPAR_XCFRAME_14_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_BCAST */
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_BCAST_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_BCAST_BASEADDR 0xf12ee000
#define XPAR_CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_BCAST_HIGHADDR 0xf12eefff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_PMC_CFI_CFRAME_BCAST */
#define XPAR_XCFRAME_15_BASEADDR 0xf12ee000
#define XPAR_XCFRAME_15_HIGHADDR 0xf12eefff
#define XPAR_XCFRAME_15_COMPATIBLE "xlnx,psv-pmc-cfi-cframe-1.0"

#define XPAR_XCFUPMC_NUM_INSTANCES 1

/* Definitions for peripheral PMC_CFU_APB_0 */
#define XPAR_PMC_CFU_APB_0_COMPATIBLE "xlnx,psv-pmc-cfu-apb-1.0"
#define XPAR_PMC_CFU_APB_0_BASEADDR 0xf12b0000
#define XPAR_PMC_CFU_APB_0_HIGHADDR 0xf12bffff

/* Canonical definitions for peripheral PMC_CFU_APB_0 */
#define XPAR_XCFUPMC_0_BASEADDR 0xf12b0000
#define XPAR_XCFUPMC_0_HIGHADDR 0xf12bffff
#define XPAR_XCFUPMC_0_COMPATIBLE "xlnx,psv-pmc-cfu-apb-1.0"

#define XPAR_XCSUDMA_NUM_INSTANCES 2

/* Definitions for peripheral DMA0 */
#define XPAR_DMA0_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_DMA0_BASEADDR 0xf11c0000
#define XPAR_DMA0_HIGHADDR 0xf11cffff
#define XPAR_DMA0_DMA_TYPE 0x1
#define XPAR_DMA0_INTERRUPTS 0x4083

/* Canonical definitions for peripheral DMA0 */
#define XPAR_XCSUDMA_0_BASEADDR 0xf11c0000
#define XPAR_XCSUDMA_0_HIGHADDR 0xf11cffff
#define XPAR_XCSUDMA_0_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_XCSUDMA_0_DMA_TYPE 0x1
#define XPAR_XCSUDMA_0_INTERRUPTS 0x4083

/* Definitions for peripheral DMA1 */
#define XPAR_DMA1_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_DMA1_BASEADDR 0xf11d0000
#define XPAR_DMA1_HIGHADDR 0xf11dffff
#define XPAR_DMA1_DMA_TYPE 0x2
#define XPAR_DMA1_INTERRUPTS 0x4084

/* Canonical definitions for peripheral DMA1 */
#define XPAR_XCSUDMA_1_BASEADDR 0xf11d0000
#define XPAR_XCSUDMA_1_HIGHADDR 0xf11dffff
#define XPAR_XCSUDMA_1_COMPATIBLE "xlnx,zynqmp-csudma-1.0"
#define XPAR_XCSUDMA_1_DMA_TYPE 0x2
#define XPAR_XCSUDMA_1_INTERRUPTS 0x4084

#define XPAR_XEMACPS_NUM_INSTANCES 2

/* Definitions for peripheral GEM0 */
#define XPAR_GEM0_COMPATIBLE "xlnx,versal-gem"
#define XPAR_GEM0_BASEADDR 0xff0c0000
#define XPAR_GEM0_HIGHADDR 0xff0c0fff
#define XPAR_GEM0_INTERRUPTS 0x4038
#define XPAR_GEM0_INTERRUPTS_1 0x4038
#define XPAR_GEM0_CLOCKS 0x31
#define XPAR_GEM0_PHY_MODE "rgmii-id"
#define XPAR_GEM0_PHY_HANDLE 0x1

/* Canonical definitions for peripheral GEM0 */
#define XPAR_XEMACPS_0_BASEADDR 0xff0c0000
#define XPAR_XEMACPS_0_HIGHADDR 0xff0c0fff
#define XPAR_XEMACPS_0_COMPATIBLE "xlnx,versal-gem"
#define XPAR_XEMACPS_0_CLOCKS 0x31
#define XPAR_XEMACPS_0_INTERRUPTS 0x4038
#define XPAR_XEMACPS_0_PHY_MODE "rgmii-id"
#define XPAR_XEMACPS_0_PHY_HANDLE 0x1

/* Definitions for peripheral GEM1 */
#define XPAR_GEM1_COMPATIBLE "xlnx,versal-gem"
#define XPAR_GEM1_BASEADDR 0xff0d0000
#define XPAR_GEM1_HIGHADDR 0xff0d0fff
#define XPAR_GEM1_INTERRUPTS 0x403a
#define XPAR_GEM1_INTERRUPTS_1 0x403a
#define XPAR_GEM1_CLOCKS 0x33
#define XPAR_GEM1_PHY_MODE "rgmii-id"
#define XPAR_GEM1_PHY_HANDLE 0x2

/* Canonical definitions for peripheral GEM1 */
#define XPAR_XEMACPS_1_BASEADDR 0xff0d0000
#define XPAR_XEMACPS_1_HIGHADDR 0xff0d0fff
#define XPAR_XEMACPS_1_COMPATIBLE "xlnx,versal-gem"
#define XPAR_XEMACPS_1_CLOCKS 0x33
#define XPAR_XEMACPS_1_INTERRUPTS 0x403a
#define XPAR_XEMACPS_1_PHY_MODE "rgmii-id"
#define XPAR_XEMACPS_1_PHY_HANDLE 0x2

#define XPAR_XGPIOPS_NUM_INSTANCES 1

/* Definitions for peripheral GPIO1 */
#define XPAR_GPIO1_COMPATIBLE "xlnx,pmc-gpio-1.0"
#define XPAR_GPIO1_BASEADDR 0xf1020000
#define XPAR_GPIO1_HIGHADDR 0xf1020fff
#define XPAR_GPIO1_INTERRUPTS 0x407a

/* Canonical definitions for peripheral GPIO1 */
#define XPAR_XGPIOPS_0_BASEADDR 0xf1020000
#define XPAR_XGPIOPS_0_HIGHADDR 0xf1020fff
#define XPAR_XGPIOPS_0_COMPATIBLE "xlnx,pmc-gpio-1.0"
#define XPAR_XGPIOPS_0_INTERRUPTS 0x407a

#define XPAR_XIICPS_NUM_INSTANCES 2

/* Definitions for peripheral I2C0 */
#define XPAR_I2C0_COMPATIBLE "cdns,i2c-r1p14"
#define XPAR_I2C0_BASEADDR 0xff020000
#define XPAR_I2C0_HIGHADDR 0xff020fff
#define XPAR_I2C0_CLOCK_FREQ 0x5f5e0a4
#define XPAR_I2C0_INTERRUPTS 0x400e
#define XPAR_I2C0_CLOCKS 0x62

/* Canonical definitions for peripheral I2C0 */
#define XPAR_XIICPS_0_BASEADDR 0xff020000
#define XPAR_XIICPS_0_HIGHADDR 0xff020fff
#define XPAR_XIICPS_0_COMPATIBLE "cdns,i2c-r1p14"
#define XPAR_XIICPS_0_CLOCK_FREQ 0x5f5e0a4
#define XPAR_XIICPS_0_CLOCKS 0x62
#define XPAR_XIICPS_0_INTERRUPTS 0x400e

/* Definitions for peripheral I2C1 */
#define XPAR_I2C1_COMPATIBLE "cdns,i2c-r1p14"
#define XPAR_I2C1_BASEADDR 0xff030000
#define XPAR_I2C1_HIGHADDR 0xff030fff
#define XPAR_I2C1_CLOCK_FREQ 0x5f5e0a4
#define XPAR_I2C1_INTERRUPTS 0x400f
#define XPAR_I2C1_CLOCKS 0x63

/* Canonical definitions for peripheral I2C1 */
#define XPAR_XIICPS_1_BASEADDR 0xff030000
#define XPAR_XIICPS_1_HIGHADDR 0xff030fff
#define XPAR_XIICPS_1_COMPATIBLE "cdns,i2c-r1p14"
#define XPAR_XIICPS_1_CLOCK_FREQ 0x5f5e0a4
#define XPAR_XIICPS_1_CLOCKS 0x63
#define XPAR_XIICPS_1_INTERRUPTS 0x400f

#define XPAR_XIOMODULE_NUM_INSTANCES 1

/* Definitions for peripheral IOMODULE0 */
#define XPAR_IOMODULE0_COMPATIBLE "xlnx,iomodule-3.1"
#define XPAR_IOMODULE0_BASEADDR 0xf0280000
#define XPAR_IOMODULE0_HIGHADDR 0xf0280fff
#define XPAR_IOMODULE0_BASEADDR_1 0xffffffffffffffff
#define XPAR_IOMODULE0_INTC_HAS_FAST 0x0
#define XPAR_IOMODULE0_INTC_BASE_VECTORS 0xf0240000
#define XPAR_IOMODULE0_INTC_ADDR_WIDTH 0x20
#define XPAR_IOMODULE0_INTC_LEVEL_EDGE 0x7fff
#define XPAR_IOMODULE0_OPTIONS 0x1
#define XPAR_IOMODULE0_CLOCK_FREQ 0x5f5e100
#define XPAR_IOMODULE0_UART_BAUDRATE 0x1c200
#define XPAR_IOMODULE0_PIT_USED_0 1
#define XPAR_IOMODULE0_PIT_USED_1 1
#define XPAR_IOMODULE0_PIT_USED_2 1
#define XPAR_IOMODULE0_PIT_USED_3 1
#define XPAR_IOMODULE0_PIT_SIZE_0 32
#define XPAR_IOMODULE0_PIT_SIZE_1 32
#define XPAR_IOMODULE0_PIT_SIZE_2 32
#define XPAR_IOMODULE0_PIT_SIZE_3 32
#define XPAR_IOMODULE0_PIT_MASK_0 4294967295
#define XPAR_IOMODULE0_PIT_MASK_1 4294967295
#define XPAR_IOMODULE0_PIT_MASK_2 4294967295
#define XPAR_IOMODULE0_PIT_MASK_3 4294967295
#define XPAR_IOMODULE0_PIT_PRESCALER_0 9
#define XPAR_IOMODULE0_PIT_PRESCALER_1 0
#define XPAR_IOMODULE0_PIT_PRESCALER_2 9
#define XPAR_IOMODULE0_PIT_PRESCALER_3 0
#define XPAR_IOMODULE0_PIT_READABLE_0 1
#define XPAR_IOMODULE0_PIT_READABLE_1 1
#define XPAR_IOMODULE0_PIT_READABLE_2 1
#define XPAR_IOMODULE0_PIT_READABLE_3 1
#define XPAR_IOMODULE0_GPO_INIT_0 0
#define XPAR_IOMODULE0_GPO_INIT_1 0
#define XPAR_IOMODULE0_GPO_INIT_2 0
#define XPAR_IOMODULE0_GPO_INIT_3 0
#define XPAR_IOMODULE0_MAX_INTR_SIZE 0x20
#define XPAR_IOMODULE0_INTC_INTR_SIZE 0x10
#define XPAR_IOMODULE0_INTC_USE_EXT_INTR 0x1
#define XPAR_IOMODULE0_INTC_POSITIVE 0xffff
#define XPAR_IOMODULE0_UART_PROG_BAUDRATE 0x1
#define XPAR_IOMODULE0_UART_DATA_BITS 0x8
#define XPAR_IOMODULE0_UART_USE_PARITY 0x0
#define XPAR_IOMODULE0_UART_ODD_PARITY 0x0
#define XPAR_IOMODULE0_UART_RX_INTERRUPT 0x1
#define XPAR_IOMODULE0_UART_TX_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_UART_RX 0x1
#define XPAR_IOMODULE0_USE_UART_TX 0x1
#define XPAR_IOMODULE0_UART_ERROR_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_FIT1 0x0
#define XPAR_IOMODULE0_FIT1_NO_CLOCKS 0x1848
#define XPAR_IOMODULE0_FIT1_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_FIT2 0x0
#define XPAR_IOMODULE0_FIT2_NO_CLOCKS 0x1848
#define XPAR_IOMODULE0_FIT2_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_FIT3 0x0
#define XPAR_IOMODULE0_FIT3_NO_CLOCKS 0x1848
#define XPAR_IOMODULE0_FIT3_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_FIT4 0x0
#define XPAR_IOMODULE0_FIT4_NO_CLOCKS 0x1848
#define XPAR_IOMODULE0_FIT4_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_PIT1 0x1
#define XPAR_IOMODULE0_PIT1_SIZE 0x20
#define XPAR_IOMODULE0_PIT1_READABLE 0x1
#define XPAR_IOMODULE0_PIT1_PRESCALER 0x9
#define XPAR_IOMODULE0_PIT1_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_PIT2 0x1
#define XPAR_IOMODULE0_PIT2_SIZE 0x20
#define XPAR_IOMODULE0_PIT2_READABLE 0x1
#define XPAR_IOMODULE0_PIT2_PRESCALER 0x0
#define XPAR_IOMODULE0_PIT2_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_PIT3 0x1
#define XPAR_IOMODULE0_PIT3_SIZE 0x20
#define XPAR_IOMODULE0_PIT3_READABLE 0x1
#define XPAR_IOMODULE0_PIT3_PRESCALER 0x9
#define XPAR_IOMODULE0_PIT3_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_PIT4 0x1
#define XPAR_IOMODULE0_PIT4_SIZE 0x20
#define XPAR_IOMODULE0_PIT4_READABLE 0x1
#define XPAR_IOMODULE0_PIT4_PRESCALER 0x0
#define XPAR_IOMODULE0_PIT4_INTERRUPT 0x1
#define XPAR_IOMODULE0_USE_GPO1 0x1
#define XPAR_IOMODULE0_GPO1_SIZE 0x3
#define XPAR_IOMODULE0_GPO1_INIT 0x0
#define XPAR_IOMODULE0_USE_GPO2 0x0
#define XPAR_IOMODULE0_GPO2_SIZE 0x20
#define XPAR_IOMODULE0_GPO2_INIT 0x0
#define XPAR_IOMODULE0_USE_GPO3 0x0
#define XPAR_IOMODULE0_GPO3_SIZE 0x20
#define XPAR_IOMODULE0_GPO3_INIT 0x0
#define XPAR_IOMODULE0_USE_GPO4 0x0
#define XPAR_IOMODULE0_GPO4_SIZE 0x20
#define XPAR_IOMODULE0_GPO4_INIT 0x0
#define XPAR_IOMODULE0_USE_GPI1 0x0
#define XPAR_IOMODULE0_GPI1_SIZE 0x20
#define XPAR_IOMODULE0_GPI1_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_GPI2 0x0
#define XPAR_IOMODULE0_GPI2_SIZE 0x20
#define XPAR_IOMODULE0_GPI2_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_GPI3 0x0
#define XPAR_IOMODULE0_GPI3_SIZE 0x20
#define XPAR_IOMODULE0_GPI3_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_GPI4 0x0
#define XPAR_IOMODULE0_GPI4_SIZE 0x20
#define XPAR_IOMODULE0_GPI4_INTERRUPT 0x0
#define XPAR_IOMODULE0_USE_IO_BUS 0x0
#define XPAR_IOMODULE0_IO_MASK 0xfffe0000
#define XPAR_IOMODULE0_FREQ 0x5f5e100
#define XPAR_IOMODULE0_IO_BASEADDR_0 4294967295
#define XPAR_IOMODULE0_IO_BASEADDR_1 4294967295

/* Canonical definitions for peripheral IOMODULE0 */
#define XPAR_XIOMODULE_0_BASEADDR 0xf0280000
#define XPAR_XIOMODULE_0_HIGHADDR 0xf0280fff
#define XPAR_XIOMODULE_0_COMPATIBLE "xlnx,iomodule-3.1"
#define XPAR_XIOMODULE_0_CLOCK_FREQ 0x5f5e100
#define XPAR_XIOMODULE_0_FIT1_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT1_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT2_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT2_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT3_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT3_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FIT4_NO_CLOCKS 0x1848
#define XPAR_XIOMODULE_0_FIT4_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_FREQ 0x5f5e100
#define XPAR_XIOMODULE_0_GPO_INIT_0 0
#define XPAR_XIOMODULE_0_GPO_INIT_1 0
#define XPAR_XIOMODULE_0_GPO_INIT_2 0
#define XPAR_XIOMODULE_0_GPO_INIT_3 0
#define XPAR_XIOMODULE_0_GPO1_SIZE 0x3
#define XPAR_XIOMODULE_0_GPO1_INIT 0x0
#define XPAR_XIOMODULE_0_GPO2_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO2_INIT 0x0
#define XPAR_XIOMODULE_0_GPO3_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO3_INIT 0x0
#define XPAR_XIOMODULE_0_GPO4_SIZE 0x20
#define XPAR_XIOMODULE_0_GPO4_INIT 0x0
#define XPAR_XIOMODULE_0_GPI1_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI1_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI2_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI2_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI3_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI3_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_GPI4_SIZE 0x20
#define XPAR_XIOMODULE_0_GPI4_INTERRUPT 0x0
#define XPAR_XIOMODULE_0_INTC_HAS_FAST 0x0
#define XPAR_XIOMODULE_0_INTC_BASE_VECTORS 0xf0240000
#define XPAR_XIOMODULE_0_INTC_ADDR_WIDTH 0x20
#define XPAR_XIOMODULE_0_INTC_LEVEL_EDGE 0x7fff
#define XPAR_XIOMODULE_0_INTC_INTR_SIZE 0x10
#define XPAR_XIOMODULE_0_INTC_USE_EXT_INTR 0x1
#define XPAR_XIOMODULE_0_INTC_POSITIVE 0xffff
#define XPAR_XIOMODULE_0_IO_MASK 0xfffe0000
#define XPAR_XIOMODULE_0_IO_BASEADDR_0 4294967295
#define XPAR_XIOMODULE_0_IO_BASEADDR_1 4294967295
#define XPAR_XIOMODULE_0_MAX_INTR_SIZE 0x20
#define XPAR_XIOMODULE_0_OPTIONS 0x1
#define XPAR_XIOMODULE_0_PIT_USED_0 1
#define XPAR_XIOMODULE_0_PIT_USED_1 1
#define XPAR_XIOMODULE_0_PIT_USED_2 1
#define XPAR_XIOMODULE_0_PIT_USED_3 1
#define XPAR_XIOMODULE_0_PIT_SIZE_0 32
#define XPAR_XIOMODULE_0_PIT_SIZE_1 32
#define XPAR_XIOMODULE_0_PIT_SIZE_2 32
#define XPAR_XIOMODULE_0_PIT_SIZE_3 32
#define XPAR_XIOMODULE_0_PIT_MASK_0 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_1 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_2 4294967295
#define XPAR_XIOMODULE_0_PIT_MASK_3 4294967295
#define XPAR_XIOMODULE_0_PIT_PRESCALER_0 9
#define XPAR_XIOMODULE_0_PIT_PRESCALER_1 0
#define XPAR_XIOMODULE_0_PIT_PRESCALER_2 9
#define XPAR_XIOMODULE_0_PIT_PRESCALER_3 0
#define XPAR_XIOMODULE_0_PIT_READABLE_0 1
#define XPAR_XIOMODULE_0_PIT_READABLE_1 1
#define XPAR_XIOMODULE_0_PIT_READABLE_2 1
#define XPAR_XIOMODULE_0_PIT_READABLE_3 1
#define XPAR_XIOMODULE_0_PIT1_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT1_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT1_PRESCALER 0x9
#define XPAR_XIOMODULE_0_PIT1_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT2_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT2_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT2_PRESCALER 0x0
#define XPAR_XIOMODULE_0_PIT2_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT3_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT3_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT3_PRESCALER 0x9
#define XPAR_XIOMODULE_0_PIT3_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_PIT4_SIZE 0x20
#define XPAR_XIOMODULE_0_PIT4_READABLE 0x1
#define XPAR_XIOMODULE_0_PIT4_PRESCALER 0x0
#define XPAR_XIOMODULE_0_PIT4_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_UART_BAUDRATE 0x1c200
#define XPAR_XIOMODULE_0_UART_PROG_BAUDRATE 0x1
#define XPAR_XIOMODULE_0_UART_DATA_BITS 0x8
#define XPAR_XIOMODULE_0_UART_USE_PARITY 0x0
#define XPAR_XIOMODULE_0_UART_ODD_PARITY 0x0
#define XPAR_XIOMODULE_0_UART_RX_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_UART_TX_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_USE_UART_RX 0x1
#define XPAR_XIOMODULE_0_USE_UART_TX 0x1
#define XPAR_XIOMODULE_0_UART_ERROR_INTERRUPT 0x1
#define XPAR_XIOMODULE_0_USE_FIT1 0x0
#define XPAR_XIOMODULE_0_USE_FIT2 0x0
#define XPAR_XIOMODULE_0_USE_FIT3 0x0
#define XPAR_XIOMODULE_0_USE_FIT4 0x0
#define XPAR_XIOMODULE_0_USE_PIT1 0x1
#define XPAR_XIOMODULE_0_USE_PIT2 0x1
#define XPAR_XIOMODULE_0_USE_PIT3 0x1
#define XPAR_XIOMODULE_0_USE_PIT4 0x1
#define XPAR_XIOMODULE_0_USE_GPO1 0x1
#define XPAR_XIOMODULE_0_USE_GPO2 0x0
#define XPAR_XIOMODULE_0_USE_GPO3 0x0
#define XPAR_XIOMODULE_0_USE_GPO4 0x0
#define XPAR_XIOMODULE_0_USE_GPI1 0x0
#define XPAR_XIOMODULE_0_USE_GPI2 0x0
#define XPAR_XIOMODULE_0_USE_GPI3 0x0
#define XPAR_XIOMODULE_0_USE_GPI4 0x0
#define XPAR_XIOMODULE_0_USE_IO_BUS 0x0

#define XPAR_XIPIPSU_NUM_INSTANCES 2

/* Definitions for peripheral IPI_PMC */
#define XPAR_IPI_PMC_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_IPI_PMC_BASEADDR 0xff320000
#define XPAR_IPI_PMC_HIGHADDR 0xff32ffff
#define XPAR_IPI_PMC_BASEADDR_1 0xff3f0200
#define XPAR_IPI_PMC_IPI_BITMASK 0x2
#define XPAR_IPI_PMC_IPI_BUF_INDEX 0x1
#define XPAR_IPI_PMC_INTERRUPTS 0x401b
#define XPAR_IPI_PMC_INTR 0x3b
#define XPAR_IPI_PMC_IPI_TARGET_COUNT 0xa
#define XPAR_IPI_PMC_0_IPI_BITMASK 0x4
#define XPAR_IPI_PMC_0_IPI_BUF_INDEX 0x2
#define XPAR_IPI_PMC_1_IPI_BITMASK 0x8
#define XPAR_IPI_PMC_1_IPI_BUF_INDEX 0x3
#define XPAR_IPI_PMC_2_IPI_BITMASK 0x10
#define XPAR_IPI_PMC_2_IPI_BUF_INDEX 0x4
#define XPAR_IPI_PMC_3_IPI_BITMASK 0x20
#define XPAR_IPI_PMC_3_IPI_BUF_INDEX 0x5
#define XPAR_IPI_PMC_4_IPI_BITMASK 0x40
#define XPAR_IPI_PMC_4_IPI_BUF_INDEX 0x6
#define XPAR_IPI_PMC_5_IPI_BITMASK 0x80
#define XPAR_IPI_PMC_5_IPI_BUF_INDEX 0x7
#define XPAR_IPI_PMC_6_IPI_BITMASK 0x200
#define XPAR_IPI_PMC_6_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_7_IPI_BITMASK 0x2
#define XPAR_IPI_PMC_7_IPI_BUF_INDEX 0x1
#define XPAR_IPI_PMC_8_IPI_BITMASK 0x100
#define XPAR_IPI_PMC_8_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_9_IPI_BITMASK 0x1
#define XPAR_IPI_PMC_9_IPI_BUF_INDEX 0x0

/* Canonical definitions for peripheral IPI_PMC */
#define XPAR_XIPIPSU_0_BASEADDR 0xff320000
#define XPAR_XIPIPSU_0_HIGHADDR 0xff32ffff
#define XPAR_XIPIPSU_0_INTR 0x3b
#define XPAR_XIPIPSU_0_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_XIPIPSU_0_IPI_BITMASK 0x2
#define XPAR_XIPIPSU_0_IPI_BUF_INDEX 0x1
#define XPAR_XIPIPSU_0_INTERRUPTS 0x401b
#define XPAR_XIPIPSU_0_IPI_TARGET_COUNT 0xa
#define XPAR_XIPIPSU_0_CH0_IPI_BITMASK 0x4
#define XPAR_XIPIPSU_0_CH0_IPI_BUF_INDEX 0x2
#define XPAR_XIPIPSU_0_CH1_IPI_BITMASK 0x8
#define XPAR_XIPIPSU_0_CH1_IPI_BUF_INDEX 0x3
#define XPAR_XIPIPSU_0_CH2_IPI_BITMASK 0x10
#define XPAR_XIPIPSU_0_CH2_IPI_BUF_INDEX 0x4
#define XPAR_XIPIPSU_0_CH3_IPI_BITMASK 0x20
#define XPAR_XIPIPSU_0_CH3_IPI_BUF_INDEX 0x5
#define XPAR_XIPIPSU_0_CH4_IPI_BITMASK 0x40
#define XPAR_XIPIPSU_0_CH4_IPI_BUF_INDEX 0x6
#define XPAR_XIPIPSU_0_CH5_IPI_BITMASK 0x80
#define XPAR_XIPIPSU_0_CH5_IPI_BUF_INDEX 0x7
#define XPAR_XIPIPSU_0_CH6_IPI_BITMASK 0x200
#define XPAR_XIPIPSU_0_CH6_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH7_IPI_BITMASK 0x2
#define XPAR_XIPIPSU_0_CH7_IPI_BUF_INDEX 0x1
#define XPAR_XIPIPSU_0_CH8_IPI_BITMASK 0x100
#define XPAR_XIPIPSU_0_CH8_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_0_CH9_IPI_BITMASK 0x1
#define XPAR_XIPIPSU_0_CH9_IPI_BUF_INDEX 0x0

/* Definitions for peripheral IPI_PMC_NOBUF */
#define XPAR_IPI_PMC_NOBUF_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_IPI_PMC_NOBUF_BASEADDR 0xff390000
#define XPAR_IPI_PMC_NOBUF_HIGHADDR 0xff39ffff
#define XPAR_IPI_PMC_NOBUF_IPI_BITMASK 0x100
#define XPAR_IPI_PMC_NOBUF_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_INTERRUPTS 0x401c
#define XPAR_IPI_PMC_NOBUF_INTR 0x3c
#define XPAR_IPI_PMC_NOBUF_IPI_TARGET_COUNT 0xa
#define XPAR_IPI_PMC_NOBUF_0_IPI_BITMASK 0x4
#define XPAR_IPI_PMC_NOBUF_0_IPI_BUF_INDEX 0x2
#define XPAR_IPI_PMC_NOBUF_1_IPI_BITMASK 0x8
#define XPAR_IPI_PMC_NOBUF_1_IPI_BUF_INDEX 0x3
#define XPAR_IPI_PMC_NOBUF_2_IPI_BITMASK 0x10
#define XPAR_IPI_PMC_NOBUF_2_IPI_BUF_INDEX 0x4
#define XPAR_IPI_PMC_NOBUF_3_IPI_BITMASK 0x20
#define XPAR_IPI_PMC_NOBUF_3_IPI_BUF_INDEX 0x5
#define XPAR_IPI_PMC_NOBUF_4_IPI_BITMASK 0x40
#define XPAR_IPI_PMC_NOBUF_4_IPI_BUF_INDEX 0x6
#define XPAR_IPI_PMC_NOBUF_5_IPI_BITMASK 0x80
#define XPAR_IPI_PMC_NOBUF_5_IPI_BUF_INDEX 0x7
#define XPAR_IPI_PMC_NOBUF_6_IPI_BITMASK 0x200
#define XPAR_IPI_PMC_NOBUF_6_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_7_IPI_BITMASK 0x2
#define XPAR_IPI_PMC_NOBUF_7_IPI_BUF_INDEX 0x1
#define XPAR_IPI_PMC_NOBUF_8_IPI_BITMASK 0x100
#define XPAR_IPI_PMC_NOBUF_8_IPI_BUF_INDEX 0xffff
#define XPAR_IPI_PMC_NOBUF_9_IPI_BITMASK 0x1
#define XPAR_IPI_PMC_NOBUF_9_IPI_BUF_INDEX 0x0

/* Canonical definitions for peripheral IPI_PMC_NOBUF */
#define XPAR_XIPIPSU_1_BASEADDR 0xff390000
#define XPAR_XIPIPSU_1_HIGHADDR 0xff39ffff
#define XPAR_XIPIPSU_1_INTR 0x3c
#define XPAR_XIPIPSU_1_COMPATIBLE "xlnx,versal-ipi-mailbox"
#define XPAR_XIPIPSU_1_IPI_BITMASK 0x100
#define XPAR_XIPIPSU_1_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_INTERRUPTS 0x401c
#define XPAR_XIPIPSU_1_IPI_TARGET_COUNT 0xa
#define XPAR_XIPIPSU_1_CH0_IPI_BITMASK 0x4
#define XPAR_XIPIPSU_1_CH0_IPI_BUF_INDEX 0x2
#define XPAR_XIPIPSU_1_CH1_IPI_BITMASK 0x8
#define XPAR_XIPIPSU_1_CH1_IPI_BUF_INDEX 0x3
#define XPAR_XIPIPSU_1_CH2_IPI_BITMASK 0x10
#define XPAR_XIPIPSU_1_CH2_IPI_BUF_INDEX 0x4
#define XPAR_XIPIPSU_1_CH3_IPI_BITMASK 0x20
#define XPAR_XIPIPSU_1_CH3_IPI_BUF_INDEX 0x5
#define XPAR_XIPIPSU_1_CH4_IPI_BITMASK 0x40
#define XPAR_XIPIPSU_1_CH4_IPI_BUF_INDEX 0x6
#define XPAR_XIPIPSU_1_CH5_IPI_BITMASK 0x80
#define XPAR_XIPIPSU_1_CH5_IPI_BUF_INDEX 0x7
#define XPAR_XIPIPSU_1_CH6_IPI_BITMASK 0x200
#define XPAR_XIPIPSU_1_CH6_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH7_IPI_BITMASK 0x2
#define XPAR_XIPIPSU_1_CH7_IPI_BUF_INDEX 0x1
#define XPAR_XIPIPSU_1_CH8_IPI_BITMASK 0x100
#define XPAR_XIPIPSU_1_CH8_IPI_BUF_INDEX 0xffff
#define XPAR_XIPIPSU_1_CH9_IPI_BITMASK 0x1
#define XPAR_XIPIPSU_1_CH9_IPI_BUF_INDEX 0x0

#define XPAR_XQSPIPSU_NUM_INSTANCES 1

/* Definitions for peripheral QSPI */
#define XPAR_QSPI_COMPATIBLE "xlnx,versal-qspi-1.0"
#define XPAR_QSPI_BASEADDR 0xf1030000
#define XPAR_QSPI_HIGHADDR 0xf1030fff
#define XPAR_QSPI_CLOCK_FREQ 0x11e1a1ed
#define XPAR_QSPI_CONNECTION_MODE 0x2
#define XPAR_QSPI_BUS_WIDTH 0x2
#define XPAR_QSPI_INTERRUPTS 0x407d
#define XPAR_QSPI_CLOCKS 0x39
#define XPAR_QSPI_QSPI_FBCLK 0x1
#define XPAR_QSPI_BAUD_RATE_DIV 0x8

/* Canonical definitions for peripheral QSPI */
#define XPAR_XQSPIPSU_0_BASEADDR 0xf1030000
#define XPAR_XQSPIPSU_0_HIGHADDR 0xf1030fff
#define XPAR_XQSPIPSU_0_BUS_WIDTH 0x2
#define XPAR_XQSPIPSU_0_BAUD_RATE_DIV 0x8
#define XPAR_XQSPIPSU_0_COMPATIBLE "xlnx,versal-qspi-1.0"
#define XPAR_XQSPIPSU_0_CLOCK_FREQ 0x11e1a1ed
#define XPAR_XQSPIPSU_0_CONNECTION_MODE 0x2
#define XPAR_XQSPIPSU_0_CLOCKS 0x39
#define XPAR_XQSPIPSU_0_INTERRUPTS 0x407d
#define XPAR_XQSPIPSU_0_QSPI_FBCLK 0x1

#define XPAR_XSDPS_NUM_INSTANCES 1

/* Definitions for peripheral SDHCI1 */
#define XPAR_SDHCI1_COMPATIBLE "xlnx,versal-8.9a"
#define XPAR_SDHCI1_BASEADDR 0xf1050000
#define XPAR_SDHCI1_HIGHADDR 0xf105ffff
#define XPAR_SDHCI1_SDIO_CLK_FREQ_HZ 0xbebc149
#define XPAR_SDHCI1_HAS_CD 0x1
#define XPAR_SDHCI1_HAS_WP 0x0
#define XPAR_SDHCI1_BUS_WIDTH 0x8
#define XPAR_SDHCI1_MIO_BANK 0x1
#define XPAR_SDHCI1_HAS_EMIO 0x0
#define XPAR_SDHCI1_SLOT_TYPE 0x4
#define XPAR_SDHCI1_IS_CACHE_COHERENT 0x0
#define XPAR_SDHCI1_CLOCKS 0x3c
#define XPAR_SDHCI1_CLK_50_SDR_ITAP_DLY 0x25
#define XPAR_SDHCI1_CLK_50_SDR_OTAP_DLY 0x4
#define XPAR_SDHCI1_CLK_50_DDR_ITAP_DLY 0x2a
#define XPAR_SDHCI1_CLK_50_DDR_OTAP_DLY 0x3
#define XPAR_SDHCI1_CLK_100_SDR_OTAP_DLY 0x3
#define XPAR_SDHCI1_CLK_200_SDR_OTAP_DLY 0x2

/* Canonical definitions for peripheral SDHCI1 */
#define XPAR_XSDPS_0_BASEADDR 0xf1050000
#define XPAR_XSDPS_0_HIGHADDR 0xf105ffff
#define XPAR_XSDPS_0_BUS_WIDTH 0x8
#define XPAR_XSDPS_0_COMPATIBLE "xlnx,versal-8.9a"
#define XPAR_XSDPS_0_CLOCKS 0x3c
#define XPAR_XSDPS_0_CLK_50_SDR_ITAP_DLY 0x25
#define XPAR_XSDPS_0_CLK_50_SDR_OTAP_DLY 0x4
#define XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY 0x2a
#define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0x3
#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0x3
#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0x2
#define XPAR_XSDPS_0_HAS_CD 0x1
#define XPAR_XSDPS_0_HAS_WP 0x0
#define XPAR_XSDPS_0_HAS_EMIO 0x0
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0x0
#define XPAR_XSDPS_0_MIO_BANK 0x1
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 0xbebc149
#define XPAR_XSDPS_0_SLOT_TYPE 0x4

#define XPAR_XSYSMONPSV_NUM_INSTANCES 1

/* Definitions for peripheral SYSMON0 */
#define XPAR_SYSMON0_COMPATIBLE "xlnx,versal-sysmon"
#define XPAR_SYSMON0_BASEADDR 0xf1270000
#define XPAR_SYSMON0_HIGHADDR 0xf1273fff
#define XPAR_SYSMON0_0_REG 0xa
#define XPAR_SYSMON0_1_REG 0xb
#define XPAR_SYSMON0_2_REG 0xc
#define XPAR_SYSMON0_3_REG 0xd
#define XPAR_SYSMON0_4_REG 0x18
#define XPAR_SYSMON0_5_REG 0x19
#define XPAR_SYSMON0_6_REG 0x1d
#define XPAR_SYSMON0_7_REG 0x1e
#define XPAR_SYSMON0_8_REG 0x22
#define XPAR_SYSMON0_9_REG 0x23
#define XPAR_SYSMON0_10_REG 0x24
#define XPAR_SYSMON0_11_REG 0x25

/* Canonical definitions for peripheral SYSMON0 */
#define XPAR_XSYSMONPSV_0_BASEADDR 0xf1270000
#define XPAR_XSYSMONPSV_0_HIGHADDR 0xf1273fff
#define XPAR_XSYSMONPSV_0_COMPATIBLE "xlnx,versal-sysmon"

#define XPAR_XTRNGPSV_NUM_INSTANCES 1

/* Definitions for peripheral PMC_TRNG */
#define XPAR_PMC_TRNG_COMPATIBLE "xlnx,psv-pmc-trng-1.0"
#define XPAR_PMC_TRNG_BASEADDR 0xf1230000
#define XPAR_PMC_TRNG_HIGHADDR 0xf123ffff

/* Canonical definitions for peripheral PMC_TRNG */
#define XPAR_XTRNGPSV_0_BASEADDR 0xf1230000
#define XPAR_XTRNGPSV_0_HIGHADDR 0xf123ffff
#define XPAR_XTRNGPSV_0_COMPATIBLE "xlnx,psv-pmc-trng-1.0"

#define XPAR_XTTCPS_NUM_INSTANCES 4

/* Definitions for peripheral TTC0 */
#define XPAR_TTC0_COMPATIBLE "cdns,ttc"
#define XPAR_TTC0_BASEADDR 0xff0e0000
#define XPAR_TTC0_HIGHADDR 0xff0e0fff
#define XPAR_TTC0_CLOCK_FREQ 0x8f0d0f7
#define XPAR_TTC0_INTERRUPTS 0x4025
#define XPAR_TTC0_INTERRUPTS_1 0x4026
#define XPAR_TTC0_INTERRUPTS_2 0x4027
#define XPAR_TTC0_TTC_CLK0_CLKSRC 0x0

/* Canonical definitions for peripheral TTC0 */
#define XPAR_XTTCPS_0_BASEADDR 0xff0e0000
#define XPAR_XTTCPS_0_HIGHADDR 0xff0e0fff
#define XPAR_XTTCPS_0_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_0_CLOCK_FREQ 0x8f0d0f7
#define XPAR_XTTCPS_0_INTERRUPTS 0x4025
#define XPAR_XTTCPS_0_TTC_CLK0_CLKSRC 0x0

/* Definitions for peripheral TTC1 */
#define XPAR_TTC1_COMPATIBLE "cdns,ttc"
#define XPAR_TTC1_BASEADDR 0xff0f0000
#define XPAR_TTC1_HIGHADDR 0xff0f0fff
#define XPAR_TTC1_CLOCK_FREQ 0x8f0d0f7
#define XPAR_TTC1_INTERRUPTS 0x4028
#define XPAR_TTC1_INTERRUPTS_1 0x4029
#define XPAR_TTC1_INTERRUPTS_2 0x402a
#define XPAR_TTC1_TTC_CLK0_CLKSRC 0x0

/* Canonical definitions for peripheral TTC1 */
#define XPAR_XTTCPS_1_BASEADDR 0xff0f0000
#define XPAR_XTTCPS_1_HIGHADDR 0xff0f0fff
#define XPAR_XTTCPS_1_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_1_CLOCK_FREQ 0x8f0d0f7
#define XPAR_XTTCPS_1_INTERRUPTS 0x4028
#define XPAR_XTTCPS_1_TTC_CLK0_CLKSRC 0x0

/* Definitions for peripheral TTC2 */
#define XPAR_TTC2_COMPATIBLE "cdns,ttc"
#define XPAR_TTC2_BASEADDR 0xff100000
#define XPAR_TTC2_HIGHADDR 0xff100fff
#define XPAR_TTC2_CLOCK_FREQ 0x8f0d0f7
#define XPAR_TTC2_INTERRUPTS 0x402b
#define XPAR_TTC2_INTERRUPTS_1 0x402c
#define XPAR_TTC2_INTERRUPTS_2 0x402d
#define XPAR_TTC2_TTC_CLK0_CLKSRC 0x0

/* Canonical definitions for peripheral TTC2 */
#define XPAR_XTTCPS_2_BASEADDR 0xff100000
#define XPAR_XTTCPS_2_HIGHADDR 0xff100fff
#define XPAR_XTTCPS_2_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_2_CLOCK_FREQ 0x8f0d0f7
#define XPAR_XTTCPS_2_INTERRUPTS 0x402b
#define XPAR_XTTCPS_2_TTC_CLK0_CLKSRC 0x0

/* Definitions for peripheral TTC3 */
#define XPAR_TTC3_COMPATIBLE "cdns,ttc"
#define XPAR_TTC3_BASEADDR 0xff110000
#define XPAR_TTC3_HIGHADDR 0xff110fff
#define XPAR_TTC3_CLOCK_FREQ 0x8f0d0f7
#define XPAR_TTC3_INTERRUPTS 0x402e
#define XPAR_TTC3_INTERRUPTS_1 0x402f
#define XPAR_TTC3_INTERRUPTS_2 0x4030
#define XPAR_TTC3_TTC_CLK0_CLKSRC 0x0

/* Canonical definitions for peripheral TTC3 */
#define XPAR_XTTCPS_3_BASEADDR 0xff110000
#define XPAR_XTTCPS_3_HIGHADDR 0xff110fff
#define XPAR_XTTCPS_3_COMPATIBLE "cdns,ttc"
#define XPAR_XTTCPS_3_CLOCK_FREQ 0x8f0d0f7
#define XPAR_XTTCPS_3_INTERRUPTS 0x402e
#define XPAR_XTTCPS_3_TTC_CLK0_CLKSRC 0x0

#define XPAR_XUARTLITE_NUM_INSTANCES 1

/* Definitions for peripheral PMC_PPU1_MDM_0 */
#define XPAR_PMC_PPU1_MDM_0_COMPATIBLE "xlnx,psv-pmc-ppu1-mdm-1.0"
#define XPAR_PMC_PPU1_MDM_0_BASEADDR 0xf0310000
#define XPAR_PMC_PPU1_MDM_0_HIGHADDR 0xf0317fff

/* Canonical definitions for peripheral PMC_PPU1_MDM_0 */
#define XPAR_XUARTLITE_0_BASEADDR 0xf0310000
#define XPAR_XUARTLITE_0_HIGHADDR 0xf0317fff
#define XPAR_XUARTLITE_0_COMPATIBLE "xlnx,psv-pmc-ppu1-mdm-1.0"

#define XPAR_XUARTPSV_NUM_INSTANCES 1

/* Definitions for peripheral SERIAL0 */
#define XPAR_SERIAL0_COMPATIBLE "arm,pl011"
#define XPAR_SERIAL0_BASEADDR 0xff000000
#define XPAR_SERIAL0_HIGHADDR 0xff000fff
#define XPAR_SERIAL0_CLOCK_FREQ 0x5f5e0a4
#define XPAR_SERIAL0_BAUDRATE 0x1c200
#define XPAR_SERIAL0_INTERRUPTS 0x4012

/* Canonical definitions for peripheral SERIAL0 */
#define XPAR_XUARTPSV_0_BASEADDR 0xff000000
#define XPAR_XUARTPSV_0_HIGHADDR 0xff000fff
#define XPAR_XUARTPSV_0_BAUDRATE 0x1c200
#define XPAR_XUARTPSV_0_COMPATIBLE "arm,pl011"
#define XPAR_XUARTPSV_0_CLOCK_FREQ 0x5f5e0a4
#define XPAR_XUARTPSV_0_INTERRUPTS 0x4012

#define XPAR_XUSBPSU_NUM_INSTANCES 1

/* Definitions for peripheral DWC3_0 */
#define XPAR_DWC3_0_COMPATIBLE "snps,dwc3"
#define XPAR_DWC3_0_BASEADDR 0xfe200000
#define XPAR_DWC3_0_HIGHADDR 0xfe20ffff
#define XPAR_DWC3_0_ENABLE_SUPERSPEED 0x0
#define XPAR_DWC3_0_INTERRUPTS 0x4016
#define XPAR_DWC3_0_INTERRUPTS_1 0x4016
#define XPAR_DWC3_0_INTERRUPTS_2 0x401a
#define XPAR_DWC3_0_INTERRUPTS_3 0x404a

/* Canonical definitions for peripheral DWC3_0 */
#define XPAR_XUSBPSU_0_BASEADDR 0xfe200000
#define XPAR_XUSBPSU_0_HIGHADDR 0xfe20ffff
#define XPAR_XUSBPSU_0_COMPATIBLE "snps,dwc3"
#define XPAR_XUSBPSU_0_ENABLE_SUPERSPEED 0x0
#define XPAR_XUSBPSU_0_INTERRUPTS 0x4016

#define XPAR_XZDMA_NUM_INSTANCES 8

/* Definitions for peripheral LPD_DMA_CHAN0 */
#define XPAR_LPD_DMA_CHAN0_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_LPD_DMA_CHAN0_BASEADDR 0xffa80000
#define XPAR_LPD_DMA_CHAN0_HIGHADDR 0xffa80fff
#define XPAR_LPD_DMA_CHAN0_DMA_MODE 0x1
#define XPAR_LPD_DMA_CHAN0_INTERRUPTS 0x403c

/* Canonical definitions for peripheral LPD_DMA_CHAN0 */
#define XPAR_XZDMA_0_BASEADDR 0xffa80000
#define XPAR_XZDMA_0_HIGHADDR 0xffa80fff
#define XPAR_XZDMA_0_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_0_DMA_MODE 0x1
#define XPAR_XZDMA_0_INTERRUPTS 0x403c

/* Definitions for peripheral LPD_DMA_CHAN1 */
#define XPAR_LPD_DMA_CHAN1_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_LPD_DMA_CHAN1_BASEADDR 0xffa90000
#define XPAR_LPD_DMA_CHAN1_HIGHADDR 0xffa90fff
#define XPAR_LPD_DMA_CHAN1_DMA_MODE 0x1
#define XPAR_LPD_DMA_CHAN1_INTERRUPTS 0x403d

/* Canonical definitions for peripheral LPD_DMA_CHAN1 */
#define XPAR_XZDMA_1_BASEADDR 0xffa90000
#define XPAR_XZDMA_1_HIGHADDR 0xffa90fff
#define XPAR_XZDMA_1_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_1_DMA_MODE 0x1
#define XPAR_XZDMA_1_INTERRUPTS 0x403d

/* Definitions for peripheral LPD_DMA_CHAN2 */
#define XPAR_LPD_DMA_CHAN2_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_LPD_DMA_CHAN2_BASEADDR 0xffaa0000
#define XPAR_LPD_DMA_CHAN2_HIGHADDR 0xffaa0fff
#define XPAR_LPD_DMA_CHAN2_DMA_MODE 0x1
#define XPAR_LPD_DMA_CHAN2_INTERRUPTS 0x403e

/* Canonical definitions for peripheral LPD_DMA_CHAN2 */
#define XPAR_XZDMA_2_BASEADDR 0xffaa0000
#define XPAR_XZDMA_2_HIGHADDR 0xffaa0fff
#define XPAR_XZDMA_2_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_2_DMA_MODE 0x1
#define XPAR_XZDMA_2_INTERRUPTS 0x403e

/* Definitions for peripheral LPD_DMA_CHAN3 */
#define XPAR_LPD_DMA_CHAN3_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_LPD_DMA_CHAN3_BASEADDR 0xffab0000
#define XPAR_LPD_DMA_CHAN3_HIGHADDR 0xffab0fff
#define XPAR_LPD_DMA_CHAN3_DMA_MODE 0x1
#define XPAR_LPD_DMA_CHAN3_INTERRUPTS 0x403f

/* Canonical definitions for peripheral LPD_DMA_CHAN3 */
#define XPAR_XZDMA_3_BASEADDR 0xffab0000
#define XPAR_XZDMA_3_HIGHADDR 0xffab0fff
#define XPAR_XZDMA_3_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_3_DMA_MODE 0x1
#define XPAR_XZDMA_3_INTERRUPTS 0x403f

/* Definitions for peripheral LPD_DMA_CHAN4 */
#define XPAR_LPD_DMA_CHAN4_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_LPD_DMA_CHAN4_BASEADDR 0xffac0000
#define XPAR_LPD_DMA_CHAN4_HIGHADDR 0xffac0fff
#define XPAR_LPD_DMA_CHAN4_DMA_MODE 0x1
#define XPAR_LPD_DMA_CHAN4_INTERRUPTS 0x4040

/* Canonical definitions for peripheral LPD_DMA_CHAN4 */
#define XPAR_XZDMA_4_BASEADDR 0xffac0000
#define XPAR_XZDMA_4_HIGHADDR 0xffac0fff
#define XPAR_XZDMA_4_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_4_DMA_MODE 0x1
#define XPAR_XZDMA_4_INTERRUPTS 0x4040

/* Definitions for peripheral LPD_DMA_CHAN5 */
#define XPAR_LPD_DMA_CHAN5_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_LPD_DMA_CHAN5_BASEADDR 0xffad0000
#define XPAR_LPD_DMA_CHAN5_HIGHADDR 0xffad0fff
#define XPAR_LPD_DMA_CHAN5_DMA_MODE 0x1
#define XPAR_LPD_DMA_CHAN5_INTERRUPTS 0x4041

/* Canonical definitions for peripheral LPD_DMA_CHAN5 */
#define XPAR_XZDMA_5_BASEADDR 0xffad0000
#define XPAR_XZDMA_5_HIGHADDR 0xffad0fff
#define XPAR_XZDMA_5_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_5_DMA_MODE 0x1
#define XPAR_XZDMA_5_INTERRUPTS 0x4041

/* Definitions for peripheral LPD_DMA_CHAN6 */
#define XPAR_LPD_DMA_CHAN6_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_LPD_DMA_CHAN6_BASEADDR 0xffae0000
#define XPAR_LPD_DMA_CHAN6_HIGHADDR 0xffae0fff
#define XPAR_LPD_DMA_CHAN6_DMA_MODE 0x1
#define XPAR_LPD_DMA_CHAN6_INTERRUPTS 0x4042

/* Canonical definitions for peripheral LPD_DMA_CHAN6 */
#define XPAR_XZDMA_6_BASEADDR 0xffae0000
#define XPAR_XZDMA_6_HIGHADDR 0xffae0fff
#define XPAR_XZDMA_6_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_6_DMA_MODE 0x1
#define XPAR_XZDMA_6_INTERRUPTS 0x4042

/* Definitions for peripheral LPD_DMA_CHAN7 */
#define XPAR_LPD_DMA_CHAN7_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_LPD_DMA_CHAN7_BASEADDR 0xffaf0000
#define XPAR_LPD_DMA_CHAN7_HIGHADDR 0xffaf0fff
#define XPAR_LPD_DMA_CHAN7_DMA_MODE 0x1
#define XPAR_LPD_DMA_CHAN7_INTERRUPTS 0x4043

/* Canonical definitions for peripheral LPD_DMA_CHAN7 */
#define XPAR_XZDMA_7_BASEADDR 0xffaf0000
#define XPAR_XZDMA_7_HIGHADDR 0xffaf0fff
#define XPAR_XZDMA_7_COMPATIBLE "xlnx,zynqmp-dma-1.0"
#define XPAR_XZDMA_7_DMA_MODE 0x1
#define XPAR_XZDMA_7_INTERRUPTS 0x4043

/* Definitions for peripheral USB0 */
#define XPAR_USB0_BASEADDR 0xff9d0000
#define XPAR_USB0_HIGHADDR 0xff9d00ff

/* Canonical definitions for peripheral USB0 */
#define XPAR_PSV_USB_0_BASEADDR 0xff9d0000
#define XPAR_PSV_USB_0_HIGHADDR 0xff9d00ff

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_0_ATCM */
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_0_ATCM_BASEADDR 0x0
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_0_ATCM_HIGHADDR 0xffff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_0_ATCM */
#define XPAR_PSV_R5_TCM_0_BASEADDR 0x0
#define XPAR_PSV_R5_TCM_0_HIGHADDR 0xffff

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_0_ATCM_LOCKSTEP */
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_0_ATCM_LOCKSTEP_BASEADDR 0xffe10000
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_0_ATCM_LOCKSTEP_HIGHADDR 0xffe1ffff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_0_ATCM_LOCKSTEP */
#define XPAR_PSV_R5_0_ATCM_LOCKSTEP_0_BASEADDR 0xffe10000
#define XPAR_PSV_R5_0_ATCM_LOCKSTEP_0_HIGHADDR 0xffe1ffff

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_0_BTCM */
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_0_BTCM_BASEADDR 0x20000
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_0_BTCM_HIGHADDR 0x2ffff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_0_BTCM */
#define XPAR_PSV_R5_TCM_1_BASEADDR 0x20000
#define XPAR_PSV_R5_TCM_1_HIGHADDR 0x2ffff

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_0_BTCM_LOCKSTEP */
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_0_BTCM_LOCKSTEP_BASEADDR 0xffe30000
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_0_BTCM_LOCKSTEP_HIGHADDR 0xffe3ffff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_0_BTCM_LOCKSTEP */
#define XPAR_PSV_R5_0_BTCM_LOCKSTEP_0_BASEADDR 0xffe30000
#define XPAR_PSV_R5_0_BTCM_LOCKSTEP_0_HIGHADDR 0xffe3ffff

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_1_ATCM */
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_1_ATCM_BASEADDR 0x0
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_1_ATCM_HIGHADDR 0xffff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_1_ATCM */
#define XPAR_PSV_R5_TCM_2_BASEADDR 0x0
#define XPAR_PSV_R5_TCM_2_HIGHADDR 0xffff

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_1_BTCM */
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_1_BTCM_BASEADDR 0x20000
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_1_BTCM_HIGHADDR 0x2ffff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_1_BTCM */
#define XPAR_PSV_R5_TCM_3_BASEADDR 0x20000
#define XPAR_PSV_R5_TCM_3_HIGHADDR 0x2ffff

/* Definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_TCM_RAM_0 */
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_TCM_RAM_0_BASEADDR 0x0
#define XPAR_CIPS_0_PSPMC_0_PSV_R5_TCM_RAM_0_HIGHADDR 0x3ffff

/* Canonical definitions for peripheral CIPS_0_PSPMC_0_PSV_R5_TCM_RAM_0 */
#define XPAR_PSV_R5_TCM_4_BASEADDR 0x0
#define XPAR_PSV_R5_TCM_4_HIGHADDR 0x3ffff

/* Definitions for peripheral PSV_R5_0_ATCM_GLOBAL */
#define XPAR_PSV_R5_0_ATCM_GLOBAL_BASEADDR 0xffe00000
#define XPAR_PSV_R5_0_ATCM_GLOBAL_HIGHADDR 0xffe0ffff

/* Canonical definitions for peripheral PSV_R5_0_ATCM_GLOBAL */
#define XPAR_PSV_TCM_GLOBAL_0_BASEADDR 0xffe00000
#define XPAR_PSV_TCM_GLOBAL_0_HIGHADDR 0xffe0ffff

/* Definitions for peripheral PSV_R5_0_BTCM_GLOBAL */
#define XPAR_PSV_R5_0_BTCM_GLOBAL_BASEADDR 0xffe20000
#define XPAR_PSV_R5_0_BTCM_GLOBAL_HIGHADDR 0xffe2ffff

/* Canonical definitions for peripheral PSV_R5_0_BTCM_GLOBAL */
#define XPAR_PSV_TCM_GLOBAL_1_BASEADDR 0xffe20000
#define XPAR_PSV_TCM_GLOBAL_1_HIGHADDR 0xffe2ffff

/* Definitions for peripheral PSV_R5_1_ATCM_GLOBAL */
#define XPAR_PSV_R5_1_ATCM_GLOBAL_BASEADDR 0xffe90000
#define XPAR_PSV_R5_1_ATCM_GLOBAL_HIGHADDR 0xffe9ffff

/* Canonical definitions for peripheral PSV_R5_1_ATCM_GLOBAL */
#define XPAR_PSV_TCM_GLOBAL_2_BASEADDR 0xffe90000
#define XPAR_PSV_TCM_GLOBAL_2_HIGHADDR 0xffe9ffff

/* Definitions for peripheral PSV_R5_1_BTCM_GLOBAL */
#define XPAR_PSV_R5_1_BTCM_GLOBAL_BASEADDR 0xffeb0000
#define XPAR_PSV_R5_1_BTCM_GLOBAL_HIGHADDR 0xffebffff

/* Canonical definitions for peripheral PSV_R5_1_BTCM_GLOBAL */
#define XPAR_PSV_TCM_GLOBAL_3_BASEADDR 0xffeb0000
#define XPAR_PSV_TCM_GLOBAL_3_HIGHADDR 0xffebffff

/*  BOARD definition */
#define XPS_BOARD_VCK190_NEWL


/*  CPU parameters definition */
#define XPAR_PSV_PMC_UNALIGNED_EXCEPTIONS 1
#define XPAR_PSV_PMC_FPU_EXCEPTION 0
#define XPAR_PSV_PMC_FSL_EXCEPTION 0
#define XPAR_PSV_PMC_DIV_ZERO_EXCEPTION 1
#define XPAR_PSV_PMC_ILL_OPCODE_EXCEPTION 1
#define XPAR_PSV_PMC_USE_STACK_PROTECTION 1
#define XPAR_PSV_PMC_FREQ 320000000
#define XPAR_PSV_PMC_USE_MSR_INSTR 1
#define XPAR_PSV_PMC_D_CACHE_LINE_SIZE 16
#define XPAR_PSV_PMC_DCACHE_ALWAYS_USED 0
#define XPAR_PSV_PMC_D_CACHE_SIZE 8192
#define XPAR_PSV_PMC_I_CACHE_LINE_SIZE 16
#define XPAR_PSV_PMC_I_CACHE_SIZE 8192
#define XPAR_PSV_PMC_ADDR_TAG_BITS 0
#define XPAR_PSV_PMC_ALLOW_DCACHE_WR 1
#define XPAR_PSV_PMC_ALLOW_ICACHE_WR 1
#define XPAR_PSV_PMC_AREA_OPTIMIZED 0
#define XPAR_PSV_PMC_CACHE_BYTE_SIZE 8192
#define XPAR_PSV_PMC_D_LMB 1
#define XPAR_PSV_PMC_I_LMB 1
#define XPAR_PSV_PMC_DCACHE_ADDR_TAG 0
#define XPAR_PSV_PMC_DCACHE_BYTE_SIZE 8192
#define XPAR_PSV_PMC_DCACHE_LINE_LEN 4
#define XPAR_PSV_PMC_DCACHE_USE_WRITEBACK 0
#define XPAR_PSV_PMC_DEBUG_ENABLED 1
#define XPAR_PSV_PMC_DYNAMIC_BUS_SIZING 0
#define XPAR_PSV_PMC_EDGE_IS_POSITIVE 1
#define XPAR_PSV_PMC_ENDIANNESS 1
#define XPAR_PSV_PMC_FSL_LINKS 0
#define XPAR_PSV_PMC_ICACHE_ALWAYS_USED 0
#define XPAR_PSV_PMC_ICACHE_LINE_LEN 4
#define XPAR_PSV_PMC_INTERCONNECT 2
#define XPAR_PSV_PMC_INTERRUPT_IS_EDGE 0
#define XPAR_PSV_PMC_MMU_DTLB_SIZE 4
#define XPAR_PSV_PMC_MMU_ITLB_SIZE 2
#define XPAR_PSV_PMC_MMU_TLB_ACCESS 3
#define XPAR_PSV_PMC_MMU_ZONES 16
#define XPAR_PSV_PMC_NUMBER_OF_PC_BRK 2
#define XPAR_PSV_PMC_NUMBER_OF_RD_ADDR_BRK 1
#define XPAR_PSV_PMC_NUMBER_OF_WR_ADDR_BRK 1
#define XPAR_PSV_PMC_OPCODE_0X0_ILLEGAL 1
#define XPAR_PSV_PMC_PVR 2
#define XPAR_PSV_PMC_PVR_USER2 0
#define XPAR_PSV_PMC_RESET_MSR 0
#define XPAR_PSV_PMC_SCO 0
#define XPAR_PSV_PMC_USE_BARREL 1
#define XPAR_PSV_PMC_USE_DCACHE 0
#define XPAR_PSV_PMC_USE_DIV 1
#define XPAR_PSV_PMC_USE_EXT_BRK 0
#define XPAR_PSV_PMC_USE_EXT_NM_BRK 0
#define XPAR_PSV_PMC_USE_EXTENDED_FSL_INSTR 0
#define XPAR_PSV_PMC_USE_FPU 0
#define XPAR_PSV_PMC_USE_HW_MUL 2
#define XPAR_PSV_PMC_USE_ICACHE 0
#define XPAR_PSV_PMC_USE_INTERRUPT 1
#define XPAR_PSV_PMC_USE_MMU 0
#define XPAR_PSV_PMC_USE_PCMP_INSTR 1
#define XPAR_PSV_PMC_D_CACHE_BASEADDR 0
#define XPAR_PSV_PMC_D_CACHE_HIGHADDR 1073741823
#define XPAR_PSV_PMC_I_CACHE_BASEADDR 0
#define XPAR_PSV_PMC_I_CACHE_HIGHADDR 1073741823
#define XPAR_PSV_PMC_REG 0
#define XPAR_PSV_PMC_BASE_VECTORS 4028891136

#define XPAR_CPU_CORE_CLOCK_FREQ_HZ 320000000

#define XPAR_MICROBLAZE_DDR_RESERVE_SA 0

#define XPAR_MICROBLAZE_ADDR_SIZE 32
#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333300

/* Number of SLRs */
#define NUMBER_OF_SLRS 0x1

/* Device ID */
#define XPAR_DEVICE_ID "xcvc1902"

#endif  /* end of protection macro */