/******************************************************************************
* Copyright (C) 2021 Xilinx, Inc.  All rights reserved.
* Copyright (C) 2022 - 2025 Advanced Micro Devices, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/

#ifndef XPM_MEMORY_POOLS_H
#define XPM_MEMORY_POOLS_H

/* Memory pool size compile-time constants */
#define MAX_TOPO_POOL_SIZE     0xA800
#define MAX_SUBSYS_POOL_SIZE   0x400
#define MAX_REQM_POOL_SIZE     0x3800
#define MAX_DEVOPS_POOL_SIZE   0x1400
#define MAX_OTHER_POOL_SIZE    0x2000
#define MAX_BOARD_POOL_SIZE    0x400
#endif /* XPM_MEMORY_POOLS_H */
